A compression-driven test access mechanism design approach

Zhang

2008 17th Asian Test Symposium

et al. 2008

1 -The increasing test-data volumes needed for the testing of system-on-chip (SOC) integrated circuits lead to long test-application times and high tester memory requirements. Efficient test planning and test-data compression are therefore needed. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. This implies that for a given set of compression schemes, there is no compression scheme that is the optimal with respect to test time reduction and test-data compression at all TAM widths. We therefore propose a technique where we integrate core wrapper design, test architecture design and test scheduling with test-data compression technique selection for each core in order to minimize the SOC test-application time and the test-data volume. Experimental results for several SOCs crafted from industrial cores demonstrate that the proposed method leads to significant reduction in test-data volume and test time.

Section: Background and Prior Workmentioning

confidence: 99%

“…A number of methods have been proposed to combine core-level test-data compression with SOC-level test planning [11,12]. As expected, these techniques show that test-data compression leads to a reduction in test time for the core-based SOC.…”

Section: Introductionmentioning

confidence: 98%

Core-Level Compression Technique Selection and SOC Test Architecture Design

Zhang

2008 17th Asian Test Symposium

et al. 2008

2011 IEEE International Test Conference

“…It selectively delivers seed data to designated modules in parallel. An XOR circuitry is used in [12] to perform compression, which in turn is employed, together with certain test application time estimates, to devise TAM design heuristics. Typically, cost-effective SoC testing requires test scheduling [17], [29].…”

Section: Introductionmentioning

confidence: 99%

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism

Janicki

Tyszer

Dutta

et al. 2011

The paper presents a new channel allocation method for higher Embedded Deterministic Test (EDT) compression in SoC designs comprising isolated cores. It employs a test data reduction technique, which allows cores to interface with ATE through an optimized number of channels. This feature is subsequently used by a new test scheduling and test access mechanisms devised for both the input and output sides. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application scheme and are reported herein.

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

“…This heuristic is guided by a test time estimation function, which is obtained using curve fitting. It is not clearly reported in [19] how the estimation function can be derived, Fig. 1.…”

mentioning

confidence: 99%

“…In [19], an XOR-network approach is used for test compression, and a compression driven TAM design heuristic is proposed. This heuristic is guided by a test time estimation function, which is obtained using curve fitting.…”

mentioning

confidence: 99%

Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

Wang

Chakrabarty

Wang³

2009

Abstract-We present a system-on-chip (SOC) testing approach that integrates test data compression, test-access mechanism/test wrapper design, and test scheduling. An efficient linear feedback shift register (LFSR) reseeding technique is used as the compression engine. All cores on the SOC share a single on-chip LFSR. At any clock cycle, one or more cores can simultaneously receive data from the LFSR. Seeds for the LFSR are computed from the care bits for the test cubes for multiple cores. We also propose a scan-slice-based scheduling algorithm that attempts to maximize the number of care bits the LFSR can produce at each clock cycle, such that the overall test application time (TAT) is minimized. This scheduling method is static in nature because it requires predetermined test cubes. We also present a dynamic scheduling method that performs test compression during test generation. Experimental results for International Symposium on Circuits and Systems and International Workshop on Logic and Synthesis benchmark circuits, as well as industrial circuits, show that optimum TAT, which is determined by the largest core, can often be achieved by the static method. If structural information is available for the cores, the dynamic method is more flexible, particularly since the performance of the static compression method depends on the nature of the predetermined test cubes.