A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells

Abstract

This paper presents TULIP, a new architecture for a binary neural network (BNN) that uses an optimal schedule for executing the operations of an arbitrary BNN. It was constructed with the goal of maximizing energy efficiency per classification. At the top-level, TULIP consists of a collection of unique processing elements (TULIP-PEs) that are organized in a SIMD fashion. Each TULIP-PE consists of a small network of binary neurons, and a small amount of local memory per neuron. The unique aspect of the binary neuron is that it is implemented as a mixed-signal circuit that natively performs the inner-product and thresholding operation of an artificial binary neuron. Moreover, the binary neuron, which is implemented as a single CMOS standard cell, is reconfigurable, and with a change in a single parameter, can implement all standard operations involved in a BNN. We present novel algorithms for mapping arbitrary nodes of a BNN onto the TULIP-PEs. TULIP was implemented as an ASIC in TSMC 40nm-LP technology. To provide a fair comparison, a recently reported BNN that employs a conventional MAC-based arithmetic processor was also implemented in the same technology. The results show that TULIP is consistently 3X more energy-efficient than the conventional design, without any penalty in performance, area, or accuracy.

Optimized register level transfer mechanism for ASIC-based memscomputing

“…For validating the performance improvement, take the recently associated model. The existing models such as Spiking Neural Network (SNN) [26], Hardware Optimized and Error Reduced Approximate Adder (HOERAA) [27], Binary Neural Network (BNN) [28], Residue Number System based Memory Loss Distributed Arithmetic (RNS-MLDA) [29].…”

CIDAN-XE: Computing in DRAM with Artificial Neurons

“…The processing element used in this paper is based on the design described in (Wagle et al, 2020). It is used to operate on multi-bit data and is referred to as Neuron Processing Element (NPE) in this paper.…”

“…An NPE can also process 4-bit operands in parallel as it consists of four ANs. Single or multi-bit addition, comparison, pooling, and ReLU operation can be scheduled on the NPE as described in (Wagle et al, 2020). (Wagle et al, 2020) used the NPE to implement binary neural networks (BNNs) with activation and weights being single bit values.…”

“…Single or multi-bit addition, comparison, pooling, and ReLU operation can be scheduled on the NPE as described in (Wagle et al, 2020). (Wagle et al, 2020) used the NPE to implement binary neural networks (BNNs) with activation and weights being single bit values. In this paper, the NPE is extended to enable multi-bit neural network operations such as multiplication, accumulation, pooling, and various activation functions.…”