A congestion-aware hybrid SRAM and STT-RAM buffer design for network-on-chip router

Abstract

Network-on-chip (NoC) offers a scalable and flexible communication infrastructure for many-cores systems. Buffers in router is used for fine-grain flow control and Quality of Service (QoS), yet it is the major contributor of area and power consumption. In this paper, we propose a hybrid buffer design with SRAM and Spin-Torque Transfer Magnetic RAM (STT-RAM) for NoC router leveraging a novel architecture combined Virtual Channel (VC) and Virtual Output Queuing (VOQ) to store congested and uncongested flow separately. Experiments demonstrates that the proposed scheme can achieve 11.8% network performance improvement and 32.9% power saving with only 8.2% area overhead degradation compared to conventional SRAM based buffer design.

2D router chip design, analysis, and simulation for effective communication

“…The results show that the OE routing method has a ratio of 2.5358, whereas the XY routing algorithm has a ratio of 2.1126. As a result, the OE routing method performs better in the 2D mesh topology [15].…”

Challenges and future directions for energy, latency, and lifetime improvements in NVMs

“…So, researchers come up with different solutions to deal with these limitations, from redesigning the conventional data structures to proposing hardware-level methods, to deploy these new technologies in their systems. Among all the challenges that Energy efficiency [4,9,13,18,[23][24][25][26][27]35] [41, [65][66][67][68][69][70][71] [ [72][73][74][75][76][77][78] NVMs face, in this paper, we focus on (1) low endurance, high energy consumption, and asymmetric read/write related problems and (2) how researchers in different communities, from databases to storage systems to embedded systems and distributed systems, overcome these limitations. Table 3 classifies the research studies from Table 2 based on their memory technologies.…”

“…So, in PCMs, there are two main operations: SET operation and RESET operation. These operations are controlled by electrical current as follows: while in the RESET operation High-power are used to place the memory cell into the high-resistance RESET state, for the SET ReRAM [8-11, 17, 18, 29, 66, 72, 75, 76] STT-RAM [8,[11][12][13][14][31][32][33] [ 41,42,63,65,70,73] NAND Flash [15,16,28,37,45,46,49] [ 51,54,56,61,64] 3D XPoint [25-27, 38, 40, 43, 44, 47, 48, 50] [ 51, 52, 55, 57-60, 62, 69] operation, moderate power but longer duration pulses are used to return the cell to the low-resistance SET state. Although PCM scales well and has write endurance comparable to that of NAND Flash (10 8 -10 9 ), which makes it a viable alternate for future high-speed storage devices.…”