A congestion-aware routing algorithm for mesh-based platform networks-on-chip

Taherkhani, Nasrin; Akbar, Reza; Safaei, Farshad; Moudi, Mehrnaz

doi:10.1016/j.mejo.2021.105145

Cited by 9 publications

(9 citation statements)

References 16 publications

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“…Because of this most global congestionaware algorithms are not proposed in recent years. However, a network is segmented into a subnet and then a global congestion-aware algorithm is implemented on them, [20] is one of these categories of an algorithm. NoC was divided into numerous subnets in this routing technique.…”

Section: Literature Reviewmentioning

confidence: 99%

“…Which is given in Table 2. In [20] different buffer levels occupied are presented by 2-bit value for congestion representation. Same congestion measure value we are using here.…”

Section: Intermediate Node Selectionmentioning

confidence: 99%

“…Mostly used synthetic traffic patterns are uniformly random, Bit-reversal, Transpose, and bit-complement. In this paper, a comparison of a suggested algorithm is done with other three similar algorithms ZARA5-16 [15], Dy-Adaptive [25], and subnet [20] under uniform random, Bit-reversal, and transpose synthetic traffic patterns at different injection rates. For a 2-D mesh 16x16 network, Fig.…”

Section: Latency and Throughput Analysismentioning

confidence: 99%

“…While using a minimal routing algorithm there is a problem arises called load balancing all over the network. ZARA [15] and ParRouting [19] partition the network, in [20] network is segmented into subnets for load balancing in the network. In our research load balancing is done by partitioning the network into two areas based on closeness centrality.…”

Section: Introductionmentioning

confidence: 99%

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An improved non-local awareness of congestion and load balanced algorithm for the communication of on chip 2D mesh-based network

Ahmed

Baig

2023

Mehran Univ. res. j. eng. technol.

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Due to advancements in multi-core design technology, IC (Integrated Circuits) designers have expanded the single chip multi-core design. A privileged way of communication effectively between these multi-cores is a Network on-chip (NoC). Design of an effective routing algorithm capable of routing data to non-congested paths is the most notable research challenge in NoC, by retrieving congestion information of non-local nodes. This research proposed an improved congestion-aware load balancing routing algorithm. Non-local or distant links congestion awareness is done by propagating congestion information via data packets. By counting number of hops from the source node, in the quadrant of the destination node, an intermediate node has been defined, and after the calculation of the least congested route to the intermediate node, this route is also stored in the data packet for source routing. Furthermore, for load balancing network is partitioned into two areas called high congested area (HCA) and low congested area (LCA). For load balancing, from HCA a node in LCA is selected as output for data packets. Comparison of the proposed algorithm is done in the form of average latency, average throughput, power consumption, and scalability analysis under synthetic traffic patterns. Under simulation experiments, it is shown improvement in an average latency and throughput of the proposed algorithm is 31.28% and 5.28% respectively, than existing.

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Section: Literature Reviewmentioning

confidence: 99%

“…Which is given in Table 2. In [20] different buffer levels occupied are presented by 2-bit value for congestion representation. Same congestion measure value we are using here.…”

Section: Intermediate Node Selectionmentioning

confidence: 99%

Section: Latency and Throughput Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An improved non-local awareness of congestion and load balanced algorithm for the communication of on chip 2D mesh-based network

Ahmed

Baig

2023

Mehran Univ. res. j. eng. technol.

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“…Firstly, it selects a sub-network according to the destination, then picks a node from its boundary as a temp node to forward the packet, and when finally the packet reaches the target sub-network, it delivers it to the destination node. Another VOLUME 4, 2016 research paper presented by Taherkhani et al [101] also follows the same strategy to segment the network into subnetwork of equal size and then uses global and local routing to improve latency and throughput. It moves packets from one sub-network to another by selecting a boundary node, and when the packet reaches its destination sub-network then moves the packet to its destination node.…”

Section: ) Congestion Propagation Network -Using Dedicated Wirementioning

confidence: 99%

Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs

et al. 2022

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Recent advances in very-large-scale integration (VLSI) technologies have offered the capability of integrating thousands of processing elements onto a single silicon microchip. Multiprocessor systems-on-chips (MPSoCs) are the latest creation of this technology evolution. Network-on-Chip (NoC) is a scalable and promising interconnection solution used by MPSoCs to achieve high performance. Routing algorithms provide a path to a packet toward the destination. For this, these algorithms should exhibit two characteristics. First, the route selection function should provide enough degree of adaptiveness to avoid network congestion. Second, it should not offer stale information on network congestion status to the neighboring routers. Many researchers have investigated network congestion and proposed techniques to control/avoid congestion. Such congestion avoidance-based algorithms significantly improve NoC performance. However, they may result in hardware overhead for side network implementation to collect congestion status. This paper reviews the selection strategies used to reduce congestion in NoC and classifies them on the technique adopted to handle and propagate congestion information. Additionally, this paper provides the implementation and analysis details of some state-of-art selection methods.

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A deep learning based latency aware predictive routing model for network‐on‐chip architectures

Sudhakar,

Reddy,

Penchalaiah

et al. 2023

Int J Communication

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SummaryNetwork on Chip (NoC) is an evolving platform for communications related applications, which are executed on a single silicon chip. There are several routing models in NoC architectures, but the accuracy of these models is limited, and the existing models are degraded because of over and under fitting issues. This research introduces the new deep learning‐based latency aware predictive routing model for on‐chip networks to route packets with better performance and power efficiency. The deep learning model used in this research is a new convolutional residual gated recurrent unit (CRGRU) with queuing theory. Moreover, the source and channel queuing delay is comprised of features to learn spatial and sequential information that improves the overall prediction accuracy. This router is modified by the intrusion of the Router States Monitor unit and the CRGRU hardware engine. The work is executed using the Xilinx platform, and the performance measures like latency and throughput are obtained by varying the network size as , , and and also varying the buffer space and length as , , and , respectively. In addition, the squared correlation coefficient (SCC) and normalized root mean square error (NRMSE) are evaluated and compared with existing learning models to validate the proposed model.

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A congestion-aware routing algorithm for mesh-based platform networks-on-chip

Cited by 9 publications

References 16 publications

An improved non-local awareness of congestion and load balanced algorithm for the communication of on chip 2D mesh-based network

An improved non-local awareness of congestion and load balanced algorithm for the communication of on chip 2D mesh-based network

Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs

A deep learning based latency aware predictive routing model for network‐on‐chip architectures

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