A content addressable memory management unit with on-chip data cache

Goksel, A. K.; Krambeck, R.H.; Thomas, P.; Tsay, M.-S.; Chen, C.Y.; Clemons, D.G.; LaRocca, F. D.; Mai, Luo

doi:10.1109/4.32012

Cited by 11 publications

(3 citation statements)

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“…The AT89S52 is a low power, high performance 8-bit CMOS microcontroller with 8k bytes of Flash programmable erasable read-only memory (PEROM). The chip-on-flash allows the programable memory to be reprogrammed in-system or by a conventional non-volatile memory programmer [12]. This system can read the input data from different sensors for different applications.…”

Section: Hardware Architecturementioning

confidence: 99%

Design of Tactical Multipurpose All–Terrain Mobile Robot

Ranjan,

Lee,

Kye

2023

ijmst

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Robotic systems that can assist soldiers in dangerous operations are essential technologies that improve safety and efficiency. This paper presents the development of mobile robots that can assist soldiers with target acquisition and surveillance on the battlefield. We have built a prototype that incorporates a firearm system that can perform shooting tasks. Our aim is to design and develop mobile robots that can cope with challenging scenarios such as terrorist attacks and rescue missions. Our robots can transmit photographic images or live streaming via a spy camera, and based on the visual information, soldiers can fire at their target with a gun mounted on the robot. We discussed the key technologies needed to design and manufacture such combat robots. Existing high-specification combat robots are expensive and inaccessible to students and researchers interested in the field. This paper reveals the technologies to develop a low-cost combat robot. This system can be used for real-time applications at an affordable price by using more advanced technology to improve its accuracy.

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Section: Hardware Architecturementioning

confidence: 99%

Design of Tactical Multipurpose All–Terrain Mobile Robot

Ranjan,

Lee,

Kye

2023

ijmst

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“…If the redial data, the cache monitor will check back in a cache location so as to accelerate the performance of memory and speed up access to data on the computer. By evaluating the performance of various system cache memory [2] [3] and [4] obtained the development of cache memory to an XOR circuit [5] [6].…”

Section: Introductionmentioning

confidence: 99%

Early result from adaptive combination of LRU, LFU and FIFO to improve cache server performance in telecommunication network

Tanwir

Hendrantoro

Affandi

2015

2015 International Seminar on Intelligent Technology and Its Applications (ISITIA)

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telecommunications system network server is a multimedia storage medium, load server is storing data transmission can be reduced with an additional caches servers which store data while making it easier for clients to access informations. The more clients to access information causing increasing caches capacity is needed deletion of caches with using a combination of algorithm LRU, LFU and FIFO Queue method, in time of the initial data to be deleted (FIFO), the other algorithm will detect if such data has the most references (LFU) or LRU algorithm so that frequently accessed data to be stored is cached it will reduce delay time, Throughput and Loss Browsing.

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“…The resequencing system should be able to handle arrivals at high megabit data rates if nanosecond logic circuits are used [28].…”

Section: Incoming Meuagamentioning

confidence: 99%

High Performance Interconnection Between High Data Rate Networks

Foudriat

Maly

Overstreet

et al.

[1992] Proceedings International Workshop on Advanced Communications and Applications for High Speed Networks

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A rjc tm Ct , [13] are becoming a reality. This paper investigates TJie paper discusses the bridge/gateway system needed \ syslsms required to interconnecting high data rate netto mterconnect a wide range of computer networks to ', works Spedal attcntion ^ directed toward providing support a wide range of user quality-of-service require-suppon for a wide variety of applications which are imments. Vie bridge/gateway must handle a wide range of plied by multimedia applications. message types including synchronous and asynchronous traffic, large, bursty messages, short, self-contained messages, time critical messages, etc. TJte paper shows that messages can be classified into three basic classes, synchronous and large and small asynchronous messages. TJie first two require call setup so that packet identification, buffer handling, etc. can be supported in the bridge/ gateway. Identification enalbes resequencing of messages at the bridge/gateway which supports interconnection between networks having large differences in packet size. Tlie third class is for messages which do not require call setup. Resequencing hardware is presented in the paper based to handle two types of resequencing problems. TJie first is for virtual parallel circuitwhich can scramble Present network interfacing supports service, between connectionless networks usually via bridges or gateways [L]. Tthe major interconnection problems has been routing. Gateways, such as in Internet, provide a compatible protocol at the network layer which forwards packets to toward their destination on the selected "best route" and, where necessary, breaks up the packet to conform to any lower layer packet length restrictions [1,2]. Thus, all stations must implement the same network layer protocol.To over come the problem of common network layer, especially where not needed the transparent bridge approach is used. Bridges generally implement some form of spanning tree algorithm which eventually gets the packet to its destination but some times via a "non-shortest" route channel bytes. Vie secondsystem is effective in handling ri> 2 , 3> 4]. Packet reformatting in bridges is minimal at both synchronous and asynchronous traffic between networks with highly differing packet sizes and data rates. Vie two other major needs for the bridge/gateway are congestion and error control. Vie paper presents a new dynamic, lossless congestion control scheme which can easily support effective error correction. Results indicate that the congestion control scheme provide close to optimal capacity under congested conditions. Under conditions where error may develop due to intewening networks which are not lossless, intermediate error recovery and correction takes 1/3 less time than equivalent end-co-end error correction under similar conditions.

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A content addressable memory management unit with on-chip data cache

Cited by 11 publications

References 1 publication

Design of Tactical Multipurpose All–Terrain Mobile Robot

Design of Tactical Multipurpose All–Terrain Mobile Robot

Early result from adaptive combination of LRU, LFU and FIFO to improve cache server performance in telecommunication network

High Performance Interconnection Between High Data Rate Networks

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