A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer

Weng, Chan-Hsiang; Wei, Tzu-An; Alpman, Erkan; Fu, Chang-Tsung; Lin, Tsung-Hsien

doi:10.1109/jssc.2016.2532345

Cited by 13 publications

(3 citation statements)

References 22 publications

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“…In and , a single resonator SAB‐based network has been proposed to implement the CT ΔΣMs with lower number of amplifiers. The implemented modulator needs relatively high GBWs amplifiers.…”

Section: Simulation Results and An Overview To The Recent Workmentioning

confidence: 99%

“…Then, in spite of same GBW requirements for amplifiers, one can easily conclude that at the circuit level, the first amplifier would need higher power consumption comparing to other ones. Also, in practice, a dynamic‐element‐matching (DEM) block is needed to mitigate the nonlinearity of current cells of first feedback DAC . Because the proposed method is almost independent to the DEM, then we do not model it in our design procedure.…”

Section: Optimum Gain‐band‐width Requirementsmentioning

confidence: 99%

“…However, in the studies of Matsukawa et al, Zanbaghi et al ., and Weng et al . , the idea of single op‐amp resonator and single‐amplifier‐biquad (SAB) network have been developed, but the idea used in our paper is different. In fact, we develop a second‐order lowpass filter by using only one amplifier.…”

Section: Introductionmentioning

confidence: 99%

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System level design and analysis of a fourth‐order continuous‐time delta‐sigma modulator using relaxed gain‐band‐width amplifiers

Hasanzadeh

Abrishamifar

2017

Circuit Theory & Apps

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Summary In this paper, based on mathematical approaches and behavioral modeling of internal blocks, an algorithm of designing a continuous‐time delta‐sigma modulator (CT ΔΣM) with aggressive noise shaping is discussed. Using proposed methods, the coefficients of modulator can be calculated directly while the finite gain‐band‐width of amplifiers and rise/fall time of digital‐to‐analog convertors (DACs) in feedback path are included in the transfer function of CT loop filter. To decrease the number of amplifiers, a unique resonator is proposed. Also, an extra feedback DAC is introduced to further reduction of gain‐band‐width requirement of last amplifier. To verify the effectiveness of proposed methods, a fourth‐order, single loop, CT ΔΣM that benefits proportional‐integrator element for compensation of excess‐loop‐delay is realized in system and behavioral circuit levels. It has a 4‐bit quantizer, over‐sampling‐ratio of 10, and out‐of‐band‐gain of 12 dB. The peaking in signal‐transfer‐function is alleviated using a feed‐forward capacitor along with proper choosing of rest coefficients. The designed modulator has 78‐dB signal‐to‐noise‐ratio; even the non‐ideal behaviors of amplifiers and DACs are involved in simulations. Independent to sampling frequency, the proposed methods can be applied to other topologies of CT ΔΣMs. Copyright © 2017 John Wiley & Sons, Ltd.

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Section: Simulation Results and An Overview To The Recent Workmentioning

confidence: 99%

Section: Optimum Gain‐band‐width Requirementsmentioning

confidence: 99%