A CORDIC-Sinusoidal Pulse Width Modulation using Silterra 0.18 &amp;#x00B5;m CMOS technology

Rongi, Mohd Asyraf; Saparon, Azilah; Marzuki, N. H.

doi:10.1109/icedsa.2010.5503098

Cited by 1 publication

(3 citation statements)

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“…In the design of the SPWM digital switching controller, the CORDIC algorithm was used to generate the reference sine-wave signal because it significantly reduces the memory storage requirement compared to the conventional sampled-points method [27,40,41]. In this design, the rotation mode of the CORDIC algorithm was implemented to calculate the sine value of the phase angle between 0 • and 90 • instead of 0 • to 360 • .…”

Section: Spwm Digital Switching Controller Design Methodsmentioning

confidence: 99%

“…By exploiting the capability of bi-directional angles of rotation (clockwise or anticlockwise) in the CORDIC algorithm, the angles can be varied from +99.4 • to −99.4 • . Details of the implementation of the CORDIC algorithm to generate the sinusoidal reference signal can be found in [40,41].…”

Section: Spwm Digital Switching Controller Design Methodsmentioning

confidence: 99%

“…For the triangle carrier-wave signal, Juarez-Abad et al (2021) also employed the sampling method by using a sampling time of 1 µs and produced 1000 points of sampled data, which were stored in a 1000-word, 32-bit BRAM [19]. However, generating the sine wave or triangular carrier wave by storing each quantized value in memory is not an area-efficient method for hardware implementation and would necessitate more memory usage if the waveforms are implemented in high resolution [20,40]. As a result, a few research papers [27,40,41] proposed the coordination rotation digital computer (CORDIC) algorithm for sine-wave generation in an FPGA-based implementation to reduce the memory requirement.…”

Section: Introductionmentioning

confidence: 99%

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Design of FPGA-Based SHE and SPWM Digital Switching Controllers for 21-Level Cascaded H-Bridge Multilevel Inverter Model

et al. 2022

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Multilevel inverters are a type of power electronic circuit that converts direct current (DC) to alternating current (AC) for use in high-voltage and high-power applications. Many recent studies on multilevel inverters have used field-programmable gate arrays (FPGAs) as a switching controller device to overcome the limitations of microcontrollers or DSPs, such as limited sampling rate, low execution speed, and a limited number of IO pins. However, the design techniques of most existing FPGA-based switching controllers require large amounts of memory (RAM) for storage of sampled data points as well as complex controller architectures to generate the output gating pulses. Therefore, in this paper, we propose two types of FPGA-based digital switching controllers, namely selective harmonic elimination (SHE) and sinusoidal pulse width modulation (SPWM), for a 21-level multilevel inverter. Both switching controllers were designed with minimal hardware complexity and logic utilisation. The designed SHE switching controller mainly consists of a four-bit finite state machine (FSM) and a 13-bit counter, while the SPWM switching controller employs a simple iterative CORDIC algorithm with a small amount of data storage requirement, a six-bit up-down counter, and a few adders. Initially, both digital switching controllers (SHE and SPWM) were designed using the hardware description language (HDL) in Verilog codes and functionally verified using the developed testbenches. The designed digital switching controllers were then synthesised and downloaded to the Intel FPGA (DE2-115) board for real-time verification purposes. For system-level verification, both switching controllers were tested on five cascaded H-Bridge circuits for a 21-level multilevel inverter model using the HDL co-simulation method in MATLAB Simulink. From the synthesised logic gates, it was found that the designed SHE and SPWM switching controllers require only 186 and 369 logic elements (LEs), respectively, which is less than 1% of the total LEs in an FPGA (Cyclone IV E) chip. The execution speed of the SHE switching controller implemented in the FPGA (Cyclone IV E) chip was found to be a maximum of 99.97% faster when compared with the microcontroller (PIC16F877A). The THD percentage of the 21-level SHE digital switching controller (3.91%) was found to be 37% less than that of the SPWM digital switching controller (6.17%). In conclusion, the proposed simplified design architectures of SHE and SPWM digital switching controllers have been proven to not only require minimal logic resources, achieve high processing speeds, and function correctly when tested on a real-time FPGA board, but also generate the desired 21-level stepped sine-wave output voltage (± 360 VPP) at a frequency of 50 Hz with low THD percentages when tested on a 21-level cascaded H-Bridge multilevel inverter model.

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Section: Spwm Digital Switching Controller Design Methodsmentioning

confidence: 99%

Section: Spwm Digital Switching Controller Design Methodsmentioning

confidence: 99%