A Core Compact Model for IGZO TFTs Considering Degeneration Mechanism

Deng, Wanling; Fang, Jielin; Wei, Xixiong; Wu, Weijing; Huang, Junkai

doi:10.1109/ted.2018.2801025

Cited by 15 publications

(4 citation statements)

References 20 publications

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“…Up to now, some models for a-IGZO TFTs have been proposed to describe current-voltage characteristics, such as the surface potential (ϕ s )-based compact model, charge-based capacitance model and unified dc/capacitance compact model [7][8][9]. Although the bandtail states and localized deep states are considered in these models for a-IGZO TFTs, the localized sub-gap density of states (DOSs) is invaluable in solving the model.…”

Section: Introductionmentioning

confidence: 99%

Electrical Stability Modeling Based on Surface Potential for a-InGaZnO TFTs under Positive-Bias Stress and Light Illumination

et al. 2023

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In this work, an electrical stability model based on surface potential is presented for amorphous In-Ga-Zn-O (a-IGZO) thin film transistors (TFTs) under positive-gate-bias stress (PBS) and light stress. In this model, the sub-gap density of states (DOSs) are depicted by exponential band tails and Gaussian deep states within the band gap of a-IGZO. Meanwhile, the surface potential solution is developed with the stretched exponential distribution relationship between the created defects and PBS time, and the Boltzmann distribution relationship between the generated traps and incident photon energy, respectively. The proposed model is verified using both the calculation results and experimental data of a-IGZO TFTs with various distribution of DOSs, and a consistent and accurate expression of the evolution of transfer curves is achieved under PBS and light illumination.

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Section: Introductionmentioning

confidence: 99%

Electrical Stability Modeling Based on Surface Potential for a-InGaZnO TFTs under Positive-Bias Stress and Light Illumination

et al. 2023

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“…However, exploration of CAAC-IGZO FET's application in radio-frequency (RF) space has so far been limited since CAAC-IGZO FETs' mobility is lower and their gate lengths longer than those of Si devices (13)(14)(15). Circuits that have been proposed so far still are in the megahertz range (16)(17)(18)(19).…”

Section: Introductionmentioning

confidence: 99%

Characteristics and Applications of CAAC-IGZO FET with Gate Length of 13nm

et al. 2020

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A field-effect transistor (FET) with a gate length of 13 nm having a c-axis aligned crystalline In-Ga-Zn oxide (CAAC-IGZO) channel was fabricated. The CAAC-IGZO FET has an off-state leakage current of 200 yA/μm, a cutoff frequency of 60GHz, and a maximum oscillation frequency of 16GHz. A CAAC-IGZO FET, though it is a small transistor, withstands voltages up to approximately 2.5 V. It also has stable current characteristics with less temperature dependence than Si devices. We have constructed an equivalent-circuit model of the CAAC-IGZO FET and designed an RF amplifier to show CAAC-IGZO FET's applicability to the GHz-range RF circuitry.

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“…However, their reliance on physical equations makes them unintuitive from both device manufacturing and circuit design perspectives because physics-based model parameters are not directly related to the device technology aspect but rather focus on the underlying physics of device operation. [8][9][10][11] Therefore, circuit designers cannot provide effective feedback on the device technology because it is not well reflected in the models. Moreover, extracting physical model parameters from devices is time consuming and requires domain expertise for each model type, delaying device, and circuit development.…”

mentioning

confidence: 99%

Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation

Eom,

Yun,

Jang

et al. 2024

Advanced Intelligent Systems

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Neural compact models are proposed to simplify device‐modeling processes without requiring domain expertise. However, the existing models have certain limitations. Specifically, some models are not parameterized, while others compromise accuracy and speed, which limits their usefulness in multi‐device applications and reduces the quality of circuit simulations. To address these drawbacks, a neural compact modeling framework with a flexible selection of technology‐based model parameters using a two‐stage neural network (NN) architecture is proposed. The proposed neural compact model comprises two NN components: one utilizes model parameters to program the other, which can then describe the current–voltage (I–V) characteristics of the device. Unlike previous neural compact models, this two‐stage network structure enables high accuracy and fast simulation program with integrated circuit emphasis (SPICE) simulation without any trade‐off. The I–V characteristics of 1000 amorphous indium–gallium–zinc‐oxide thin‐film transistor devices with different properties obtained through fully calibrated technology computer‐aided design simulations are utilized to train and test the model and a highly precise neural compact model with an average IDS error of 0.27% and R2 DC characteristic values above 0.995 is acquired. Moreover, the proposed framework outperforms the previous neural compact modeling methods in terms of SPICE simulation speed, training speed, and accuracy.

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A Core Compact Model for IGZO TFTs Considering Degeneration Mechanism

Cited by 15 publications

References 20 publications

Electrical Stability Modeling Based on Surface Potential for a-InGaZnO TFTs under Positive-Bias Stress and Light Illumination

Electrical Stability Modeling Based on Surface Potential for a-InGaZnO TFTs under Positive-Bias Stress and Light Illumination

Characteristics and Applications of CAAC-IGZO FET with Gate Length of 13nm

Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation

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