A cosimulation methodology for HW/SW validation and performance estimation

Abstract

Cosimulation strategies allow us to simulate and verify HW/SW embedded systems before the real platform is available. In this field, there is a large variety of approaches that rely on different communication mechanisms to implement an efficient interface between the SW and the HW simulators. However, the literature lacks a comprehensive methodology which addresses the need for integrating and synchronizing heterogeneous simulators, like, for example, the SystemC simulation kernel for HW modules and an instruction set simulator for SW applications, without being intrusive for the HW and SW descriptions involved in the simulation. In this context, this article presents, compares, and integrates in a system-level framework two different co-simulation strategies for modeling, analyzing, and validating the performance of a HW/SW embedded system. Moreover, for both of them, a mechanism is proposed to provide an accurate time synchronization of the HW/SW communication. The first strategy is intended to provide an early cosimulation environment where HW/SW interaction can be validated without involving the operating system. The communication is implemented between a single SW task and a SystemC description of an HW module by exploiting the features of the remote debugging interface of a debugger (the GNU GDB), and by modifying the SystemC simulation kernel. On the other hand, the second strategy is intended to be used in further development steps, when the operating system is introduced to validate the cosimulation between HW modules and multitasking SW applications. In this approach, the communication is implemented via interrupts by using the features offered by the operating system. Experimental results are reported on two different case studies to analyze and compare the effectiveness of both the approaches

Host-compiled simulation of multi-core platforms

“…The ISS kernel is integrated into the overall TLM backplane through a thin wrapper that relays all I/O and interrupts between the simulated processor and the external TLM environment [28], [29]. Internally, the ISS kernel can include a separate scheduler that simulates processor-internal parallelism, e.g.…”

System-level co-simulation for embedded systems

“…4 The main goal of the simulation is to provide an abstraction of the real world with the most flexibility needed in the modeling phase. 5,6 Indeed, there is an increasing need for customized systems. Customization has many advantages, e.g., software has given products improved capabilities.…”

A formal support for homogeneous simulation of heterogeneous embedded systems

“…Thus, to preserve component reuse, several co-simulation frameworks have been proposed [15], [16], [17], where, for the implementation of a virtual system prototype, an SLDL is applied in combination with an abstract canonical realtime operating system and/or an instruction set simulator, and/or a simulation engine for continuous behaviors. However, co-simulation assemblies heterogeneous components without providing a rigorous formal support, thus making integration and validation very hard tasks.…”

“…On the contrary, bottom-up methodologies and component reuse are supported by several co-simulation frameworks [15], [16], [17], [16] for the implementation of virtual system prototypes. A system level language, like SystemC, is applied in combination with an abstract canonical real-time operating system and/or an instruction set simulator, and/or a simulation engine for continuous behaviors.…”