A cost-effective context memory structure for dynamically reconfigurable processors

Suzuki, Motohiro; Hasegawa, Yohei; Tuan, Vu Manh; Abe, Sachiko; Amano, Hideharu

doi:10.1109/ipdps.2006.1639433

Cited by 8 publications

(5 citation statements)

References 9 publications

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“…Compression techniques are a classic method that can alleviate memory bandwidth bottlenecks [145][146][147]. These works mainly compress the configuration binaries sent to CGRAs offline with common compression algorithms, e.g., Run Length coding, Huffman coding, arithmetic coding and LZSS coding.…”

Section: Trend 4: Efficient Memory Systemmentioning

confidence: 99%

A Survey of Coarse-Grained Reconfigurable Architecture and Design

et al. 2019

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As general-purpose processors have hit the power wall and chip fabrication cost escalates alarmingly, coarsegrained reconfigurable architectures (CGRAs) are attracting increasing interest from both academia and industry, because they offer the performance and energy efficiency of hardware with the flexibility of software. However, CGRAs are not yet mature in terms of programmability, productivity, and adaptability. This article reviews the architecture and design of CGRAs thoroughly for the purpose of exploiting their full potential. First, a novel multidimensional taxonomy is proposed. Second, major challenges and the corresponding state-of-the-art techniques are surveyed and analyzed. Finally, the future development is discussed. CCS Concepts: • Computer systems organization → Reconfigurable computing; • Hardware → Reconfigurable logic and FPGAs; • Theory of computation → Models of computation;

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Section: Trend 4: Efficient Memory Systemmentioning

confidence: 99%

A Survey of Coarse-Grained Reconfigurable Architecture and Design

et al. 2019

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“…For a decade, many dynamically reconfigurable architectures have been developed but only a few can be considered as multi-context architectures, as they locally store one or more parallel contexts. NEC-DRP [7] is a massively parallel processor architecture. Reconfiguration processes are managed by a central manager which can select one futur context from 16 multi-contextmemories.…”

Section: Related Workmentioning

confidence: 99%

Efficient and Flexible Dynamic Reconfiguration for Multi Context Architectures

Lallet¹,

Pillement²,

Sentieys³

2020

JICS

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Dynamic reconfiguration is possible on both fine-grain and coarse-grain architectures. One of the used methodology used consists in the use of multi-context architectures. Unfortunately, the multiple contexts bring power and area overhead. This paper introduces the Dynamic Unifier and reConfigurable blocK (DUCK) concept, a new structure to perform efficiently dynamic reconfiguration on both custom designed fine-grain and coarse grain architectures. The DUCK allows to separate the configuration path and the configuration registers which facilitates simultaneous configuration and computing steps. The reconfiguration process is presented in detail, and synthesis results are given for different structures. Our solution is finally validated with the implementation of a WCDMA (Wideband Code Division Multiple Access) receiver on a multi-context embedded FPGA and on the dynamically reconfigurable processor DART. This implementation demonstrates the interest and the efficiency of the use of dynamic reconfiguration and the proposed flexible structure.

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“…In the hybrid one, while a part of the contexts are statically reconfigurable, the others are dynamically reconfigurable, like RaPiD. From a context size perspective, evolution of the configuration has taken place over three periods along with the increasing complexity of applications: singlecontext [18,19], multi-context [20][21][22], and configuration cache [12,23]. The number of operations in computational kernels is smaller, several times larger and many times larger than the dimension of the array in the three periods respectively.…”

Section: Introductionmentioning

confidence: 99%

Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture

Liu

Wang

Yin

et al. 2014

Sci. China Inf. Sci.

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Using the coarser operand grain and simplified interconnection patterns, CGRA (coarse grained reconfigurable architectures) has been proven to be energy efficient in several specific domains. As we know, the speed at which the contexts are applied to a PEA (processing element array) directly determines the performance of CGRA. In this paper, the design space in CGRA is further developed from the configuration granularity perspective by one middle-grained configuration granularity-the row-based configuration mechanism (RCM). The most prominent feature of the RCM is that a large DFG (data flow graph) can be mapped onto a small array in once reconfiguration, which is carried out on a row-by-row basis. Compared with an ordinary DFGpartitioning solution, the reconfiguration time and the data transfer time are well reduced. Furthermore, the proposed RCM offers much more efficient storage for the contexts. Compared with the DFG partitioning solution, the performance is boosted from 2.6% to 57.8%, while the area penalty is only 4.79% and the power penalty is only 7.22%. The RCM has been used in one reconfigurable processor called REMUS HPA (reconfigurable multi-media system, high performance version advanced). REMUS HPA has been implemented on a 50.5 mm 2 silicon with TSMC 65 nm technology. Simulation shows that 1920×1088@37 fps can be achieved for H.264 high-profile decoding when exploiting a 200 MHz working frequency. Compared with the high performance version of XPP (one commercial reconfigurable processor), the performance is 247% boosted.

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A cost-effective context memory structure for dynamically reconfigurable processors

Abstract: Abstract

Cited by 8 publications

References 9 publications

A Survey of Coarse-Grained Reconfigurable Architecture and Design

A Survey of Coarse-Grained Reconfigurable Architecture and Design

Efficient and Flexible Dynamic Reconfiguration for Multi Context Architectures

Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture

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