A cost model for partial dynamic reconfiguration

Rullmann,; Merker,

doi:10.1109/icsamos.2008.4664862

Cited by 9 publications

(3 citation statements)

References 9 publications

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“…In any case, the overhead of reconfigurations is important to consider in the design process. This has been shown in many recent works [Rullmann and Merker(2008), Duhem et al(2012)Duhem, Muller, and Lorenzini], but reconfiguration delays are not the only issue. The energy cost of DPR is also an important design parameter to manage, especially to ensure actual energy gains from its utilization.…”

Section: State Of the Artmentioning

confidence: 75%

Power consumption models for the use of dynamic and partial reconfiguration

Bonamy

Bilavarn

Chillet

et al. 2014

Microprocessors and Microsystems

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Minimizing the energy consumption and silicon area are usually two major challenges in the design of battery-powered embedded computing systems. Dynamic and Partial Reconfiguration (DPR) opens up promising prospects with the ability to reduce jointly performance and area of compute-intensive functions. However, partial reconfiguration management involves complex interactions making energy benefits very difficult to analyze. In particular, it is essential to realistically quantify the energy loss since the reconfiguration process itself introduces overheads. This paper addresses this topic and presents a detailed investigation of the power and energy costs associated to the different operations involved with the DPR capability. From actual measurements considering a Xilinx ICAP reconfiguration controller, results highlight other components involved in DPR power consumption, and lead to the proposition of three power models of different complexity and accuracy tradeoffs. Additionally, we illustrate the exploitation of these models to improve the analysis of DPR energy benefits in a realistic application example.

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Section: State Of the Artmentioning

confidence: 75%

Power consumption models for the use of dynamic and partial reconfiguration

Bonamy

Bilavarn

Chillet

et al. 2014

Microprocessors and Microsystems

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“…So, we have to calculate hardware unit configuration time (T f ) and multiplexer configuration time T mux to use in the input DFGs in the synthesis techniques and compare the results of the techniques with each other. After obtaining the bit-streams of hardware units and multiplexers using ISE 10.2, their configuration times were approximated as: configuration time = [(size of bit-stream)/(FPGA Virtex5-xcv5vlx configuration clock frequency)] [5]. The configuration clock frequency 100 MHz was used, in our experiment.…”

Section: Resultsmentioning

confidence: 99%

“…The configuration time is proportional to the length of the configuration bit-stream, and the speed of the configuration interface [5]. Reducing the length of the configuration bit-stream consequently reduces the module configuration time [6].…”

Section: Introductionmentioning

confidence: 99%

Efficient datapath merging for the overhead reduction of run-time reconfigurable systems

2010

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High latencies in FPGA reconfiguration are known as a major overhead in run-time reconfigurable systems. This overhead can be reduced by merging multiple data flow graphs representing different kernels of the original program into a single (merged) datapath that will be configured less often compared to the separate datapaths scenario. However, the additional hardware introduced by this technique increases the kernels execution time. In this paper, we present a novel datapath merging technique that reduces both the configuration and execution times of kernels mapped on the reconfigurable fabric. Experimental results show up to 13% reduction in the configuration and execution times of kernels from media-bench workloads, compared to previous art on datapath merging. When compared to conventional high-level synthesis algorithms, our proposal reduces kernels configuration and execution times by up to 48%.

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