A critical re-evaluation of the usefulness of R-D framework in predicting NBTI stress and recovery

Mahapatra, S.; Islam, Ahmad E.; Deora, S.; Maheta, V.D.; Joshi, K.; Jain, Ankit; Alam, Muhammad Ashraful

doi:10.1109/irps.2011.5784544

Cited by 91 publications

(95 citation statements)

References 26 publications

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“…Note that for a particular ΔV IT , D2 device shows slightly higher ΔV T than the 1:1 correlation line, while a somewhat larger ΔV T is observed for device D4, which is consistent with relatively larger ΔN HT contribution for device D4 having N in the gate insulator stack. Larger magnitude of hole trapping during NBTI stress in gate insulators containing N is a well-known result and reported by various groups [13][14][15]50].…”

Section: Hole Trapping During Nbtimentioning

confidence: 76%

“…However, as discussed in Chaps. 2 and 4, TDDB has much larger V G acceleration factor compared to NBTI [15], and for HKMG MOSFETs, the stress V G gets divided between the IL and High-K layers. Therefore, for moderate values of stress V G , trap generation in HKMG devices measured by DCIV can be largely associated to the NBTI process.…”

Section: Trap Generation During Nbtimentioning

confidence: 99%

“…In spite of these experimental evidences, some reports have suggested hole trapping in pre-existing traps (ΔN HT ) as the only NBTI mechanism [19][20][21][22][23], which is definitely not correct. Similarly, reports suggesting ΔN IT as the exclusive NBTI mechanism [10,11] are also not correct, as they cannot explain ultra-fast threshold voltage shift (ΔV T ) measurements [20,24,25] and gate insulator process dependence of NBTI [13][14][15]. As of today, the prevailing notion of NBTI mechanism involves contribution from both ΔN IT and ΔN HT ; although some have suggested strong coupling or correlation between the two processes [26], most reports suggest that they are independent and mutually uncorrelated [5,9,[13][14][15][16][17][18][27][28][29][30][31][32][33][34][35].…”

Section: Introductionmentioning

confidence: 98%

“…2 for accessing the density of process related and generated traps respectively before and after BTI stress. Note that direct characterization techniques such as Charge Pumping (CP) [6] and Gated Diode (or DCIV) [7] have been used in several reports to provide irrefutable proof of interface trap generation (ΔN IT ) for NBTI stress in SiON [5,[7][8][9][10][11][12][13][14][15] and HKMG [5,[16][17][18] p-MOSFETs. In spite of these experimental evidences, some reports have suggested hole trapping in pre-existing traps (ΔN HT ) as the only NBTI mechanism [19][20][21][22][23], which is definitely not correct.…”

Section: Introductionmentioning

confidence: 99%

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Physical Mechanism of BTI Degradation—Direct Estimation of Trap Generation and Trapping

Mukhopadhyay

Mahapatra

2015

Fundamentals of Bias Temperature Instability in MOS Transistors

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In this chapter, direct characterization techniques have been used to access the trap generation and trapping subcomponents of BTI degradation in HKMG MOSFETs having different gate stack processes. Generation of new traps is estimated using DCIV for NBTI stress and both DCIV and SILC for PBTI stress respectively in p-and n-channel MOSFETs. Flicker noise is used to estimate the density of process related pre-existing gate insulator traps responsible for hole and electron trapping respectively during NBTI and PBTI stress. The spatial and energetic locations of generated traps for NBTI and PBTI stress are identified. The time, bias, and temperature dependencies of trap generation obtained using the DCIV technique are compared between NBTI and PBTI stress, while these parameters obtained using DCIV and SILC techniques are compared for PBTI stress. The relative dominance of trap generation and trapping on NBTI and PBTI threshold voltage degradation is estimated for different gate insulator processes. IntroductionFrom a practical point of view of technology qualification, it is important to know the magnitude of Bias Temperature Instability (BTI) at end-of-life of devices and hence of circuits and products under normal use condition. Estimation of Negative BTI (NBTI) and Positive BTI (PBTI) respectively in p-and n-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) is usually done by stressing the devices at higher than normal gate bias (V G = V G-STR ) and measuring the resulting device parametric degradation with minimal impact of recovery artifacts. Different "recovery-free" measurement techniques have been discussed in Chap. 2. As mentioned before, stress tests are usually performed for few hours or

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Section: Hole Trapping During Nbtimentioning

confidence: 76%

Section: Trap Generation During Nbtimentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Physical Mechanism of BTI Degradation—Direct Estimation of Trap Generation and Trapping

Mukhopadhyay

Mahapatra

2015

Fundamentals of Bias Temperature Instability in MOS Transistors

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“…For a H 2 diffusion based model, n ¼ 1=6 and for a H based model n ¼ 1=4. However, recent experiments recognize H as the dominant diffusion species [84]. b m is the fraction parameter of the recovery.…”

Section: Transistor Aging Analysismentioning

confidence: 99%