A critique of length and bias dependent constraints for 1T-DRAM operation through RFET

Abstract

Capacitorless dynamic memory (1T-DRAM) operation in a reconfigurable transistor (RFET) is critically governed by different lengths associated with the architecture. These lengths consisting of ungated region (LUG), control gate (LCG), polarity gate (LPG), storage region length (LS), and total length (LT) can be sensitive to the fabrication process, and hence, critical for 1T-DRAM. This work presents an insightful critique of the above mentioned lengths for realising optimal 1T-DRAM performance. It is shown that RFET with highest values of LS/LT and LCG/LT shows good short channel immunity but does not necessarily ensure enhanced 1T-DRAM metrics. Results indicate that for a fixed LT, retention time (RT) can vary over a wide range (550 ms to 8.7 s) depending on the values of LS/LT and LCG/LT, and hence, appropriate optimization is imperative. The work contributes towards better understanding and optimizing LCG/LT to ensure improved 1T-DRAM metrics in terms of enhanced retention (> 64 ms), acceptable sense margin (> 6 µA/µm), current ratio (> 104) with low values of read (2 ns) and write (1 ns) time to further extend multi-functional facets of nanoscale RFETs for memory applications. In addition, the effect of traps, process sensitivity, reduced number of voltage levels, and disturbance caused by shared word line/bit line are also analysed in this work. Results indicate that state ‘0’ of the cell sharing bit line (BL) with the selected cell is strongly affected by BL disturbance. Word line (WL) disturbance primarily impacts state ‘1’ of the cell sharing WL with selected cell (only for write 1 and read operations).

Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications

“…1(a). 16) There are a total of six gates in RFET1 (ii) Conventional twin-gate RFET architecture which consists of two electrically connected CGs and 2 independent aligned PGs (referred to as conventional twin gate RFET) as shown in Fig. 1(b).…”

“…RFET1 shows both reconfigurable and feasible DRAM operations. 16) However, conventional twin gate RFET [Fig. 1(b)] can show reconfigurable features but memory operation is not feasible.…”

“…The programming of state 1 (W '1') in the device is carried out through the generation of excess holes (n h1 ) in the device by the positive feedback mechanism initiated through impact ionization 16) in RFET1 whereas, in RFET2, W '1' mechanism has been executed through tunneling of holes across the Schottky barrier along with impact ionization. 18) Therefore, a positive PG bias is essential in RFET1 (to enable tunneling of electrons for impact ionization) in contrast to a negative front PG bias in RFET2 (to enable tunneling hole from metal to semiconductor).…”

“…The previous works on 1T-DRAM have mainly focused on enhancing retention characteristics. 16) However, a practical implementation requires critical evaluation in terms of speed, retention, scalability, routing complexity, and power consumption, all of which are essential for highperformance embedded 1T-DRAM.…”

Complementary Doped Source-Based Reconfigurable Schottky Diode as an Equivalence Logic Gate

“…Various RFETs have been proposed to improve conduction current, improve integration, and simplify processes. − Compared with complementary metal-oxide-semiconductor field-effect transistor (MOSFET) technology, RFET technology has a significant advantage that it can use fewer devices to realize various logic gates. − With the macro background that CMOS technology will reach the physical limit in the next decade, it is increasingly difficult to improve chip performance solely by reducing device size. Therefore, the RFET has become a research hotspot this year. − The common RFET simultaneously forms a Schottky barrier between the source/drain (S/D) electrode and the conduction and valence bands of dopingless semiconductors. − The tunneling effect is generated by adjusting the program gate voltage, then the S/D resistance generated by the Schottky barrier is reduced, and the carrier type gathered in the S/D region is selected by changing the polarity of the voltage; thus, the conduction type of the device is configured. The control gate is used to regulate the formation of carrier channels.…”