A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories

Zambelli, Cristian; Indaco, Marco; Fabiano, M.; Carlo, Stefano Di; Prinetto, P.; Olivo, P.; Bertozzi, D.

doi:10.1109/date.2012.6176622

Cited by 22 publications

(23 citation statements)

References 15 publications

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“…• adaptability, i.e., a fixed correction capability ECC schema versus a variable one can be chosen [21], [26];…”

Section: A System Configuratormentioning

confidence: 99%

“…• read/program/erase elementary physical operations specifications (e.g., program verify algorithm [21]); • elementary operation timing and power consumptions, with the possibility of defining time or aging dependent values;…”

Section: A System Configuratormentioning

confidence: 99%

“…Its timings and power consumptions are summarized in Table I and are referred to a standard ISPP programming algorithm [21]. The reliability model used to evaluate the RBER is the default one, i.e.…”

Section: A Experimental Setupmentioning

confidence: 99%

See 2 more Smart Citations

Ef<sup>3</sup>S: An evaluation framework for flash-based systems

Carlo

Galfano

Indaco

et al. 2013

2013 IEEE 19th International on-Line Testing Symposium (IOLTS)

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NAND Flash memories are gaining popularity in the development of electronic embedded systems for both consumer and mission-critical applications. NAND Flashes crucially influence computing systems development and performances. EF 3 S, a framework to easily assess NAND Flash based memory systems performances (reliability, throughput, power), is presented. The framework is based on a simulation engine and a running environment which enable developers to assess any application impact. Experimental results show functionality of the framework, analysing several performance-reliability tradeoffs of an illustrative system.

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“…• adaptability, i.e., a fixed correction capability ECC schema versus a variable one can be chosen [21], [26];…”

Section: A System Configuratormentioning

confidence: 99%

Section: A System Configuratormentioning

confidence: 99%

See 1 more Smart Citation

Ef<sup>3</sup>S: An evaluation framework for flash-based systems

Carlo

Galfano

Indaco

et al. 2013

2013 IEEE 19th International on-Line Testing Symposium (IOLTS)

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“…Technology can be hardened [2][3][4][5][6][7][8], hardware architectures may include redundancy [9][10][11][12][13][14][15][16][17][18][19], and finally all software layers may implement error detection and recovery mechanisms [20][21][22][23][24][25][26]. On the one hand, this enables designers to apply cross-layer holistic design approaches to manage errors in their systems.…”

Section: Introductionmentioning

confidence: 99%

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview

Vallero

Tselonis

Foutris

et al. 2015

Microprocessors and Microsystems

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International audienceAdvanced computing systems realized in forthcoming technologies hold the promise of a significant increase of computational capabilities. However, the same path that is leading technologies toward these remarkable achievements is also making electronic devices increasingly unreliable. Developing new methods to evaluate the reliability of these systems in an early design stage has the potential to save costs, produce optimized designs and have a positive impact on the product time-to-market

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“…Although encoding BCH is fairly straightforward, performing the decoding steps is much more complex (Zambelli et al 2012). System designers must balance the high complexity of BCH decoders with their overall system requirements (Strukov 2006).…”

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confidence: 99%

Optimization of multi-channel BCH error decoding for common cases

Dill¹,

Shrivastava²,

Oh³

2015

2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)

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Error correcting systems have put increasing demands on system designers, both due to increasing error correcting requirements and higher throughput targets. These requirements have led to greater silicon area, power consumption and have forced system designers to make trade-offs in Error Correcting Code (ECC) functionality. Solutions to increase the efficiency of ECC systems are very important to system designers and have become a heavily researched area.Many such systems incorporate the Bose-Chaudhuri-Hocquenghem (BCH) method of error correcting in a multi-channel configuration. BCH is a commonly used code because of its configurability, low storage overhead, and low decoding requirements when compared to other codes. Multi-channel configurations are popular with system designers because they offer a straightforward way to increase bandwidth. The ECC hardware is duplicated for each channel and the throughput increases linearly with the number of channels. The combination of these two technologies provides a configurable and high throughput ECC architecture.This research proposes a new method to optimize a BCH error correction decoder in multi-channel configurations. In this thesis, I examine how error frequency effects the utilization of BCH hardware. Rather than implement each decoder as a single pipeline of independent decoding stages, the channels are considered together and served by a pool of decoding stages. Modified hardware blocks for handling common cases are included and the pool is sized based on an acceptable, but negligible decrease in performance. i This thesis's experimental approach examines multi-channel configurations found in typical NAND flash systems. My experimental data shows that the proposed pooled group approach requires significantly fewer hardware blocks than a traditional multi-channel configuration. By allowing a 2% performance degradation and sizing the decoding pool appropriately, the scheme reduces hardware area by 47%-71% and dynamic power by 44%-59%.Additionally, I examined what improvements were possible with the improved design using the same hardware area as the traditional implementation. My experiments show that an improved throughput of 3x-5x can be achieved or NAND flash lifetime can be extended by 1.4x-4.5x. Dr. Shrivastava has provided invaluable input into both my research and my writing.

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A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories

Cited by 22 publications

References 15 publications

Ef<sup>3</sup>S: An evaluation framework for flash-based systems

Ef<sup>3</sup>S: An evaluation framework for flash-based systems

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview

Optimization of multi-channel BCH error decoding for common cases

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