2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) 2013
DOI: 10.1109/dft.2013.6653585
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A cross-layer fault-tolerant design method for high manufacturing yield and system reliability

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Cited by 1 publication
(2 citation statements)
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“…Hence, designers have to build the circuit simulator using some design software tools (e.g., HSPICE, Simulink) to evaluate the performance function ( ) and estimate yield by simulation runs [22,23]. However, this kind of simulationbased tolerance design (e.g., Monte Carlo methods) requires numerous circuit simulations and computationally expensive analysis runs [2][3][4][5][6]. In the following section, instead of using a circuit simulator, we will build a BRB system to model the performance function by running as few simulations as possible and using experts' knowledge.…”
Section: Problem Formulationmentioning
confidence: 99%
See 1 more Smart Citation
“…Hence, designers have to build the circuit simulator using some design software tools (e.g., HSPICE, Simulink) to evaluate the performance function ( ) and estimate yield by simulation runs [22,23]. However, this kind of simulationbased tolerance design (e.g., Monte Carlo methods) requires numerous circuit simulations and computationally expensive analysis runs [2][3][4][5][6]. In the following section, instead of using a circuit simulator, we will build a BRB system to model the performance function by running as few simulations as possible and using experts' knowledge.…”
Section: Problem Formulationmentioning
confidence: 99%
“…On the other hand, circuit reliability is closely linked to its yield, namely, only those products with high yield would have high reliability. So, tolerance design and yield optimization are also the effective ways to improve circuit reliability [4].…”
Section: Introductionmentioning
confidence: 99%