A cryogenic 0.35 μm CMOS technology BSIM3.3 model for space instrumentation: Application to a bandgap design

Varizat, Laurent; Sou, Gérard; Mansour, Malik; Alison, Dominique

doi:10.1109/maes.2018.170149

Cited by 4 publications

(1 citation statement)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…liquid helium temperature (LHT) 4.2 K [7]- [9]. Physical and electrical properties of various CMOS technologies under ultra-low temperatures have been investigated [10]- [20]. To design CMOS circuits for cryogenic applications, industry-standard transistor models compatible with ultra-low temperatures are essential.…”

Section: Introductionmentioning

confidence: 99%

Towards an Improved Model for 65-nm CMOS at Cryogenic Temperatures

Jie

Schormans

Demosthenous

2020

2020 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

Cryogenic CMOS is a crucial subcomponent of quantum-technological applications, particularly as control electronics for quantum computers. Simulation is an important first step in designing any CMOS circuit. However, the standard BSIM4.5 model is only applicable for temperatures between 230 K and 420 K. In this work, N-type MOSFETs with different dimensions in a 65-nm CMOS technology were characterized at room temperature and liquid helium temperature (4.2 K). These measurements were compared with corresponding simulations from the BSIM4.5 model. A model of drain current in the triode region was constructed, where key parameters, such as threshold voltage and effective mobility, were modified. By adjusting these temperature-dependent parameters, the modified model predicted the triode region currents with an error reduced to 7.6%. Thus, the modified model can be utilized to simulate transistor behavior in the triode region at cryogenic temperatures.

show abstract

Section: Introductionmentioning

confidence: 99%

Towards an Improved Model for 65-nm CMOS at Cryogenic Temperatures

Jie

Schormans

Demosthenous

2020

2020 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

A wide-temperature range (77–400 K) CMOS low-dropout voltage regulator system

Kayihan

Inam

Doğan

et al. 2020

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

Thermal Analysis of the Solar Orbiter PHI Electronics Unit

Torralbo

Pérez-Grande

Gasent-Blesa

et al. 2020

IEEE Trans. Aerosp. Electron. Syst.

View full text Add to dashboard Cite

This paper presents the thermal design of the electronics unit of the instrument Polarimetric Helioseismic Imager, onboard the European Space Agency mission Solar Orbiter. The thermal design procedure, along with the problems encountered during this design phase, and the solutions found to fix them are described, proving in this way the thermal feasibility and robustness of the unit. Its final thermal behaviour, obtained from thermal analyses correlated with data from thermal tests performed in a vacuum environment, is presented.

show abstract

A cryogenic 0.35 μm CMOS technology BSIM3.3 model for space instrumentation: Application to a bandgap design

Cited by 4 publications

References 15 publications

Towards an Improved Model for 65-nm CMOS at Cryogenic Temperatures

Towards an Improved Model for 65-nm CMOS at Cryogenic Temperatures

A wide-temperature range (77–400 K) CMOS low-dropout voltage regulator system

Thermal Analysis of the Solar Orbiter PHI Electronics Unit

Contact Info

Product

Resources

About