A cryogenic SRAM based arbitrary waveform generator in 14 nm for spin qubit control

Abstract

Realization of qubit gate sequences require coherent microwave control pulses with programmable amplitude, duration, spacing and phase. We propose an SRAM based arbitrary waveform generator for cryogenic control of spin qubits. We demonstrate in this work, the cryogenic operation of a fully programmable radio frequency arbitrary waveform generator in 14 nm FinFET technology. The waveform sequence from a control processor can be stored in an SRAM memory array, which can be programmed in real time. The waveform pattern is converted to microwave pulses by a source-series-terminated digital to analog converter. The chip is operational at 4 K, capable of generating an arbitrary envelope shape at the desired carrier frequency. Total power consumption of the AWG is 40-140 mW at 4 K, depending upon the baud rate. A wide signal band of 1-17 GHz is measured at 4 K, while multiple qubit control can be achieved using frequency division multiplexing at an average spurious free dynamic range of 40 dB. This work paves the way to optimal qubit control and closed loop feedback control, which is necessary to achieve low latency error mitigation and correction in future quantum computing systems.

Unveiling Enhanced Trade-offs in SRAM-based Memory Arrays for Cryogenic CMOS Technology

“…Higher throughput, lower latency, and improved quantum control of CMOS-based control circuits have shown immense potential for scaled-up QCs [10], [23], [24], [27]. In these studies, researchers/engineers have actively used the SRAM as storage elements.…”

“…As the SRAM is able to deliver ultra-fast operating speed, it becomes the obvious choice for memory in cryogenic CMOS circuits. There have been multiple reports on the uses of SRAM at cryogenic temperatures [10], [22]- [24], [27]. For example, [22]- [24] have utilized the on-chip SRAM as an envelope memory to store the pulse shaping information such as amplitude and phase modulation to control/readout the qubits.…”

A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

“…Furthermore, the cryo-CMOS controllers will require memories for several distinct functions covering a wide range of access rates (read and write operations per second) and write/read (W /R) ratios, ranging from high-speed lookup tables for generating the waveforms for qubit control (multi-GHz, W /R = 0) [15], [16], [17] to low-speed buffer queues for the quantum-algorithm instructions (sub-MHz, W /R = 1) [9]. Static memories (SRAMs) are well-suited for high access-rate applications but they suffer from excessive operation energy and limited density.…”

A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing

“…So far, cryo-CMOS circuits have been placed at the 4-K stage to control and read out the qubits [14], [15], [16], [17], [18], [19], while (de)multiplexers are designed for operating at the mK stage to reduce the amount of interconnect between qubit and controller [20], [21]. Moreover, hot qubits operating with high gate fidelities at temperatures above 1 K are being developed to completely close the temperature gap between the electronics and qubits, thus improving the scalability of future quantum computers [22], [23].…”