A current-mode spiking neural classifier with lumped dendritic nonlinearity

Abstract

We present the current mode implementation of a spiking neural classifier with lumped square law dendritic nonlinearity. It has been shown earlier that such a system with binary synapses can be trained with structural plasticity algorithms to achieve comparable classification accuracy with less synaptic resources than conventional algorithms. Hence, in our address event based implementation, we save 2 − 12X memory resources in storing connectivity information. The chip fabricated in 0.35µm CMOS has 8 dendrites per cell and uses two opposing cells per class to cancel common mode inputs. Preliminary results show the chip is functional and dissipates 30nW of static power per neuronal cell and 422pJ/spike. 978-1-4799-8391-9/15/$31.00 ©2015 IEEE

An accelerated analog neuromorphic hardware system emulating NMDA- and calcium-based non-linear dendrites

“…The presented implementation is also inherently scalable in the framework of the BrainScaleS system. Neuromorphic hardware concepts based on non-linear dendrites have also been previously reported [26] [27], demonstrating the viability of the concept for pattern classification. This paper will present an extension of the BrainScaleS Adaptive-Exponential Integrate-and-Fire (AdEx) neuron model [28] that allows the replication of coincidence detection between basal and apical dendritic segments similar to those observed in experiments [29].…”

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“…Whenever V m > V th , the neuron asynchronously fires a post-synaptic spike S post of duration t p and then resets to zero. The I&F neuron circuit from [13] is used for SPICE simulation, with the memory trace T pre/post generated by T pre/post = K (t) * S pre/post where K(t) is the spike convolution kernel. The circuit is thus Globally Asynchronous Locally Synchronous since the dendritic branch outputs are synchronous but the neuronal firings are asynchronous.…”

Learning spike time codes through supervised and unsupervised structural plasticity

“…We presented that the σ µ of I 0 , τ s and cb ni for the worst case scenario are 13%, 10.1% and 18% respectively. The mismatch of the LIF neuron circuit proposed in [288] was captured by variations in the firing threshold V thr , the σ µ of which was computed to be 12.5%. Lastly, the nonidealities of the c n pj calculator block is modeled as a multiplicative constant (cc ni ).…”

“…The main blocks needed in these designs are DPI synapse, squaring circuit for implementing the dendritic nonlinearity, neuron block and the c pj calculator which have been described in Chapter 3. We have fabricated an array of NNLDs and presented the results in [288]. However, this chip does not support on-chip testing and the learnt connections have to be downloaded from a computer.…”