A current-shaping technique for static MOS current-mode logic prescalers

Shi, Jian; Taishan, Mo; Ma, Can; Ye, Tianchun

doi:10.1587/elex.10.20120887

Cited by 2 publications

(1 citation statement)

References 4 publications

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“…Although several topologies are available for prescaler in several GHz range, including current-mode logic (CML), injection-locked prescaler, true single-phase clocked logic and extended TSPC (ETSPC) logic. CML prescalers provide the highest speed over other topologies, and consume high power [1,2]. They are used only for high frequency where other topologies cannot operate.…”

Section: Introductionmentioning

confidence: 99%

A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler

Jiang

Huang

2017

IEICE Electron. Express

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A novel low-power high-speed true single-phase clock-based (TSPC) divide-by-2/3 prescaler is presented. Compared with the conventional topologies, one of the precharge stages in the TSPC flip-flops is eliminated, and the number of switching stages is reduced to 5. The prescaler is implemented in a standard 0.18-µm CMOS process. It achieves the maximum operating frequency of 5.7 GHz with a measured power consumption of 0.95 mW and 0.98 mW in divide-by-3 mode and divide-by-2 mode, respectively, when operated at 1.5-V power supply.

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Section: Introductionmentioning

confidence: 99%

A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler

Jiang

Huang

2017

IEICE Electron. Express

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High-Speed Wide-Range True-Single-Phase-Clock CMOS Dual Modulus Prescaler

Gao

Chen

et al. 2020

Electronics

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This manuscript presents two novel low-power high-speed true-single-phase-clock (TSPC) prescalers with division ratios of 2/3 and 4/5, respectively, in a standard 90-nm CMOS technology. The logic gates incorporated between the D-flip-flops (DFFs) of a conventional 2/3 prescaler are modified to reduce the propagation delay and hence increase the maximum operating frequency. The measurement results show that the proposed divide-by-2/3 and divide-by-4/5 prescalers can operate up to 17 GHz and 15.3 GHz, respectively, which increase by 5.4 GHz and 4.3 GHz compared with conventional TSPC prescalers. The power of the proposed divide-by-2/3 prescaler is 0.67 mW and 0.92 mW, and 0.87 mW and 1.06 mW for the proposed divide-by-4/5 prescaler. The chip occupies an area of 20 × 35 μm2 and 20 × 50 μm2 for the proposed divide-by-2/3 and divide-by-4/5 prescalers.

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A current-shaping technique for static MOS current-mode logic prescalers

Cited by 2 publications

References 4 publications

A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler

A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler

High-Speed Wide-Range True-Single-Phase-Clock CMOS Dual Modulus Prescaler

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