A Data-Centric Accelerator for High-Performance Hypergraph Processing

PhGraph: A High-Performance ReRAM-Based Accelerator for Hypergraph Applications

“…A hypergraph is typically represented in the bipartite representation format [2], [7], [8], which represents each hyperedge as a distinct vertex and connects the vertex with its incident vertices. Thus, as shown in Fig.…”

“…1) Inefficiencies of Existing Hypergraph Solutions: Recently, many hypergraph processing frameworks developed on CPUs and ASICs have been proposed to improve parallelism [2], data locality [7], programming productivity [8], and communication overheads [1]. However, these earlier solutions are still inadequate in addressing the memory bottleneck arising in hypergraph processing.…”

“…Similarly, the latter utilizes the newly activated hyperedges to update vertices using a vertex update function. Previous studies [7], [8] have shown that hypergraph processing is typically memory-bound. Recent solutions, based on CPUs [1] and ASICs [7], [8], improve the locality of hypergraph processing by exploiting the intrinsic hypergraph structure overlap.…”

“…Previous studies [7], [8] have shown that hypergraph processing is typically memory-bound. Recent solutions, based on CPUs [1] and ASICs [7], [8], improve the locality of hypergraph processing by exploiting the intrinsic hypergraph structure overlap. However, they remain inadequate in addressing the memory bottleneck arising in hypergraph processing.…”

“…However, they remain inadequate in addressing the memory bottleneck arising in hypergraph processing. Taking the state-of-the-art hypergraph processing accelerator XuLin [8] as a reference, especially for large hypergraphs, off-chip memory accesses can still be up to 80.19% of the total running time (as discussed in Section II-C).…”