A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications

Turker, Didem; Khatri, Sunil P.; Sánchez-Sinencio, E.

doi:10.1109/tcsi.2010.2103170

Cited by 58 publications

(34 citation statements)

References 28 publications

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“…This circuit consumes less power compared to the circuits made in the other publications mentioned in Table III with the exception of [12] where the circuit was designed with 0.13 µ technology and powered by a 1.2 V value voltage.…”

Section: Most Publications Mentioned Inmentioning

confidence: 97%

Low Power Low Jitter 0.18 CMOS Ring VCO Design with Strategy based on EKV3.0 Model

Ayed¹,

Ghariani²

2017

ijacsa

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Abstract-In this paper, the design of micro-power CMOS ring VCO with minimum jitter intended for a concept of frequency synthesizer in biotelemetry systems is studied. A design procedure implemented in MATLAB is described for a circuit realization with TSMC 0.18μm CMOS technology. This conventional design methodology based on EKV3.0 model is clearly suited to the challenges of analog circuits design with reduced channel width. Measures realized with ADS confirmed methodology capability to circuit sizing respecting the specifications of application. The designed ring VCO operates at a central frequency of 433MHz in ISM band with an amplitude of oscillation equal to 500 mV. The integration area was intrinsic (without buffers and without external capacitances). The simulated phase noise is about -108 dBc/Hz at 1MHz, the value of rms jitter is 44.8 ps and the power consumption of the designed VCO is 6.37 mW @ 433 MHz.

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Section: Most Publications Mentioned Inmentioning

confidence: 97%

Low Power Low Jitter 0.18 CMOS Ring VCO Design with Strategy based on EKV3.0 Model

Ayed¹,

Ghariani²

2017

ijacsa

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“…In bypassing multiplier, any line or section can be crippled if the comparing bit of the multiplier or multiplicand is zero [9], [10], [11], [12], [13]. This procedure diminishes the exchanging exercises of the multiplier and subsequently the power utilization is decreased.…”

Section: Bypassing Multipliermentioning

confidence: 99%

“…Contrasted with bypassing multiplier this multiplier performed better as far as power sparing and lesser postponement. George Economakos et al (2010) [12] composed a multiplier by consolidating the Wallace tree and segment bypassing procedure. This blended engineering have a noteworthy power and postpone diminishment like the Ko Chi Kuo and Chi Wen Chou (2006) [10] outline.…”

Section: Bypassing Multipliermentioning

confidence: 99%

Review on Various Multipliers Designs in VLSI

Mahendra¹

2018

IJRASET

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Among all the math tasks that exist, a processor consume a large portion of its time and hardware assets in doing multiplication when contrasted with different activities like addition and subtraction. In this paper similar examination is done of four multipliers to be specific, Array multiplier, Modified booth multiplier, Wallace tree multiplier and modified BoothWallace tree multiplier based of different execution parameters like speed, area, power and circuit complexity. It is important to plan a fast multiplier in VLSI in order to upgrade framework execution and system performance. Low Power VLSI circuit has turned out to be imperative standard for planning the vitality proficient electronic outlines for high performance and compact gadgets. In the majority of DSP application the basic activities are the multiplication. Multiplier is the most valuable task required in many hardware computation. Productive usage of multipliers is required in numerous applications. Working of a framework relies upon the execution of multiplier along these lines multipliers to be quick and expend less zone in equipment. In this paper, near comparision of various multipliers is done.

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“…In literature, various topologies have been proposed for the design of differential delay cells. Some of them can be found in [6]- [8].…”

Section: Ring Oscillator Designmentioning

confidence: 99%

3.6 GHz CMOS ring oscillator with low tune voltage sensitivity and temperature compensation

Özsema

Demirci

Leblebici

2015

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP &Amp; International Symposium on System-on-Chip (SoC)

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Abstract-In this paper we present the design of a temperature compensated low-tune-voltage-sensitive CMOS ring oscillator in 40nm standard CMOS technology. The oscillator has an overall frequency range from 3.1 GHz to 3.6 GHz. The effect of temperature variations on the frequency span has been tuned out by an IPTAT (inversely proportional to absolute temperature) current reference. In this work, using a coarse-fine tuning mechanism lowers the tune range sensitivity of the oscillator, which is usually represented as KV CO . The achieved KV CO is around 490 MHz/V with 400 mV tune voltage sweep. The area and the power consumption of the ring oscillator are 0.0056 mm 2 and 0.9 mW.

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A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications

Cited by 58 publications

References 28 publications

Low Power Low Jitter 0.18 CMOS Ring VCO Design with Strategy based on EKV3.0 Model

Low Power Low Jitter 0.18 CMOS Ring VCO Design with Strategy based on EKV3.0 Model

Review on Various Multipliers Designs in VLSI

3.6 GHz CMOS ring oscillator with low tune voltage sensitivity and temperature compensation

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