A decimal squarer with efficient partial product generation

Lin, Kuan Jen; Chiu, Y.C.; Lin, Tzu‐Hao

doi:10.1109/vlsisoc.2010.5642662

Cited by 1 publication

(2 citation statements)

References 15 publications

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“…Different types of BCD or radix-10 multipliers have been designed by researchers to enhance BCD multiplication performance. signed digit radix-10 BCD multiplication using a multi-operand adder structure [6] offers improvements in performance in comparison with conventional BCD multiplier. Available binary-to-BCD converter uses for BCD digits multiplier (BDM) in [7], Gorgin's [7] multiplier design was based on the truth table for conversion of binary number into BCD digits and develops a new combinational design architecture for implementation on FPGA.…”

Section: Introductionmentioning

confidence: 99%

“…Multi-operand adder trees [6] implementation using state of art VLSI may results complex irregular layouts of BCD multiplier as compare with binary compressor trees and carry-save adders. PPR tree and ODDS base BCD multiplier [10,11] was limited for unsigned number multiplication only, with signed-digit and self-complementing codes theirs ODDS converters fail to convert the BCD to binary and vice-versa.…”

Section: Introductionmentioning

confidence: 99%

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High-speed radix-10 multiplication using partial shifter adder tree-based convertor

Malviya¹

2021

TELKOMNIKA

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A radix-10 multiplication is the foremost frequent operations employed by several monetary business and user-oriented applications, decimal multiplier using in state of art digital systems are significantly good but can be upgraded with time delay and area optimization. This work is proposed a more area and time delay optimized new design of overloaded decimal digit set (ODDS) architecture-based radix-10 multiplier for signed numbers. Binary coded decimal (BCD) to binary followed by binary multiplication and finally binary to BCD conversion are 3 major modules employed in radix-10 multiplication. This paperwork presents a replacement technique for binary coded decimal (BCD) to binary and vice-versa convertors in radix-10 multiplication. A novel addition tree structure called as partial shifter adder (PSA) tree-based approach has been developed for BCD to binary conversion, and it is used to add partially generated products. To meet our major concern i.e. speed, we need particular high-speed multiplication, hence the proposed PSA based radix-10 multiplier is using vertical cross binary multiplication and concurrent shifterbased addition method. The design has been tested on 45nm technology-based Zynq-7 field programmable gate array (FPGA) devices with a 6-input lookup table (LUTs). A combinational implementation maps quite well into the slice structure of the Xilinx Zynq-7 families field programmable gate array. The synthesis results for a Zynq-7 device indicate that our design outperforms in terms of the area and time delay.

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Section: Introductionmentioning

confidence: 99%