A decoupled bit shifting technique using data encoding/decoding for DRAM redundancy repair

Abstract

Redundancy repairs are commonly used to support fault tolerance in DRAM systems and recently, the processor performance has been greatly improved, so DRAM access latency has become an important issue. However, existing redundancy repairs using shift logic have difficulty in further reducing the latency due to their design limitations. In this paper, we propose a novel, decoupled bit shifting technique that uses data encoding and decoding to resolve this limitation. Our technique decouples the conventional shifting logic into two units, a bit selection vector generator (BSVG) and a data manipulation unit (DMU), to reduce the latency overhead of the shifting logic. Our technique can apply the BSVG in parallel with other logic consuming long latency operations, thereby reducing the total latency compared to conventional shifting logic. We implement both serial and parallel approaches to demonstrate that the parallel approach performs significantly better than the serial one in terms of delay, area, and dynamic power consumption. The experimental results show that our bit shifting technique is applicable for redundancy repair technique in state-of-the-art DRAM architectures.

Memory built-in self-repair and correction for improving yield: a review

“…Further, the latency suffers severely when data width increases as the delay is linearly proportional to the number of bits. Choi et al [54] presented an architecture to reduce access latency by employing a parallel approach. It uses an encoder and decoder for arranging data to memory as a separate unit, as shown in Figure 11.…”

“…Figure 11. Parallel for faulty element replacement with redundant element [54] Im et al [19] proposed using multiple BISR controllers and accessing fuse data in parallel. This approach helps in 2 ways.…”

Memory test and repair technique for SoC based devices

“…The proposed MTC and BISR are developed to integrate with the SoC design, and which results in a small hardware overhead. It became significant when it compares with the memory controllers available in SoC [2,14,17] and the BISR block [13,[15][16]23] of the existing approaches. The proposed MTC and BISR blocks stand better in terms of area overhead and power consumption to test and repair the memories under SoC when compared with existing methods.…”