A decoupled non-SSA global register allocation using bipartite liveness graphs

Abstract

Register allocation is an essential optimization for all compilers. A number of sophisticated register allocation algorithms have been developed over the years. The two fundamental classes of register allocation algorithms used in modern compilers are based on Graph Coloring (GC) and Linear Scan (LS). However, these two algorithms have fundamental limitations in terms of precision. For example, the key data structure used in GC-based algorithms, the interference graph, lacks information on the program points at which two variables may interfere. The LS-based algorithms make local decisions regarding spilling, and thereby trade off global optimization for reduced compile-time and space overheads. Recently, researchers have proposed Static Single Assignment (SSA)-based decoupled register allocation algorithms that exploit the live-range split points of the SSA representation to optimally solve the spilling problem. However, SSA-based register allocation often requires extra complexity in repairing register assignments during SSA elimination and in addressing architectural constraints such as aliasing and ABI encoding; this extra overhead can be prohibitively expensive in dynamic compilation contexts.This article proposes a decoupled non-SSA-based global register allocation algorithm for dynamic compilation. It addresses the limitations in current algorithms by introducing a Bipartite Liveness Graph (BLG)-based register allocation algorithm that models the spilling phase as an optimization problem on the BLG itself and the assignment phase as a separate optimization problem. Advanced register allocation optimizations such as move coalescing, live-range splitting, and register class handling are also performed along with the spilling and assignment phases. In the presence of register classes, we propose a bucket-based greedy heuristic for assignment that strikes a balance between spill-cost and register class constraints. We present experimental evaluation of our BLG-based register allocation algorithm and compare it with production-quality register allocators in Jikes RVM and LLVM. ACM Reference Format:Barik, R., Zhao, J., and Sarkar, V. 2013. A decoupled non-SSA global register allocation using bipartite liveness graphs. ACM Trans.

Bytewise Register Allocation

“…While they can be generalized to handle some architectural irregularities [24,26], they cannot handle the extreme irregularities and aliasing resulting from bytewise register allocation well. Many of the recent graph-coloring approaches are decoupled, i. e. they handle register assignment and spilling in separate stages of the register allocator [26,4,8]. There are some approaches based on integer linear programming (ILP) [13,11] and partitioned Boolean quadratic programming (PBQP) [23,16].…”

Using the SSA-Form in a Code Generator

“…In particular, liveness analysis, unrollingbased loop optimizations, and exploitation of special instructions or addressing modes benefit significantly from the SSA form. On the other hand, the SSA form does not apply after register allocation, and there is still debate as to whether it should be used in the register allocator [3].…”