A deep learning methodology to proliferate golden signoff timing

Abstract

Abstract-Signoff timing analysis remains a critical element in the IC design flow. Multiple signoff corners, libraries, design methodologies, and implementation flows make timing closure very complex at advanced technology nodes. Design teams often wish to ensure that one tool's timing reports are neither optimistic nor pessimistic with respect to another tool's reports. The resulting "correlation" problem is highly complex because tools contain millions of lines of black-box and legacy code, licenses prevent any reverse-engineering of algorithms, and the nature of the problem is seemingly "unbounded" across possible designs, timing paths, and electrical parameters.In this work, we apply a "big-data" approach to the timer correlation problem. We develop a machine learning-based tool, Golden Timer eXtension (GTX), to correct divergence in flip-flop setup time, cell arc delay, wire delay, stage delay, and path slack at timing endpoints between timers. We propose a methodology to apply GTX to two arbitrary timers, and we evaluate scalability of GTX across multiple designs and foundry technologies / libraries, both with and without signal integrity analysis. Our experimental results show reduction in divergence between timing tools from 139.3ps to 21.1ps (i.e., 6.6×) in endpoint slack, and from 117ps to 23.8ps (4.9× reduction) in stage delay. We further demonstrate the incremental application of our methods so that models can be adapted to any outlier discrepancies when new designs are taped out in the same technology / library. Last, we demonstrate that GTX can also correlate timing reports between signoff and design implementation tools.

Machine-Learning-Based Multi-Corner Timing Prediction for Faster Timing Closure

“…In [10], Kahng et al use an ML predictor to predict signal integrity (SI) mode timing from the timing reports of non-SI mode analysis. Han et al have developed a machine learning-based tool, GTX [11], to correct divergence between two STA tools. A learning approach is proposed in [12] to estimate wire slew and delay, reducing the number of invocations of the signoff STA tool.…”

“…In parasitic interconnect, resistance and capacitance are the most important variables, and thus, the influence of parasitic interconnect on timing is defined as the RC-Corner. In this paper, we perform research based on the timing results from 14 corners, which are marked with Corner ID (1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14) along with the specific parameter values shown in Table 1.…”