A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs

Dhia, Arwa Ben; Pagliarini, Samuel; Naviner, Lírida Alves de Barros; Mehrez, Habib; Matherat, Philippe

doi:10.1016/j.microrel.2013.06.014

Cited by 7 publications

(3 citation statements)

References 21 publications

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“…Dhia et al [24] proposed a multiplexer for nanometer designs that is area-efficient. The leaf cell of any FPGA will be a 2-1 multiplexer.…”

Section: Finfet Device and Technologymentioning

confidence: 99%

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A 16 nm FinFET circuit with triple function as digital multiplexer, active-high and active-low output decoder for high-performance SRAM architecture

Battini¹,

Sivani²

2022

Semicond. Sci. Technol.

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This paper presents a FinFET based Single Circuit (FSC) used to realize Active-High output Decoder (AHD), Active-Low output Decoder (ALD), and Digital Multiplexer. The input signal is traversed through a single transmission gate irrespective of the size of FSC is the uniqueness of the proposed multiplexer. The new architectures of FSC use an equal number of n-FinFET and p-FinFET devices, requiring few transistors compared to CMOS designs. Three novel circuits are created using various logic styles following the same architecture. The FSC is compared with the similar circuits, and on average, the results of power dissipation and delay in the worst case show that FSC is better by 14\%, and 18\%, respectively. An FSC is created and extensively simulated at 16nm FinFET technology using Eldo software. All the circuits are designed for 0.75V, 1V, and 1.25V and are stimulated with multiple input frequencies. The proposed circuit is best suitable for row address decoders and column multiplexers of SRAM.

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“…Dhia et al [24] proposed a multiplexer for nanometer designs that is area-efficient. The leaf cell of any FPGA will be a 2-1 multiplexer.…”

Section: Finfet Device and Technologymentioning

confidence: 99%

“…The ouput expressions for the active-low output decoder (ALD) are complementary to AH0, AH1, AH2 and AH3. An area-efficient multiplexer for lookup tables of FPGAs was designed in [24]. The authors of previous works presented various combinations of cells using decoders, and multiplexer cells can be designed separately.…”

Section: Finfet Device and Technologymentioning

confidence: 99%

A 16 nm FinFET circuit with triple function as digital multiplexer, active-high and active-low output decoder for high-performance SRAM architecture

Battini¹,

Sivani²

2022

Semicond. Sci. Technol.

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“…Their methods are based on using unused resources, which is used in fault tolerance. Dhia et al (2013), the authors used redundancy method for bypassing faults in FPGAs. Their fault tolerant method depends on shifting, which is useful for reconfiguration.…”

Section: Related Researchmentioning

confidence: 99%

Reconfiguring Evolved Circuits Using Controller: A Real Time Approach

Krishna¹

2014

Journal of Computer Science

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FPGA is a device that contains a matrix of reconfigurable gate arrays that can implement different complex functions and also vary structurally. In this study, a novel method of reconfigurable circuit switching action is done with the help of a controller. BPSK Modulation application is chosen to demonstrate the reconfigurable action. When an event occurs the context/core switching is done at both input and output and also preserving the structural and functional relationship. The reconfiguration ability of FPGA with an embedded core performing the switching in real time is the focus of this study. A controller running on Linux platform is used along with the FPGA core. In this study, we propose a real time approach for reconfiguring evolved circuits using controller. It has an adaptive hardware that can continuously change in response to the input data and there by perform reconfiguration. Here the reconfiguration process is achieved by using a real time controller which gives a command to the FPGA core (ALTERA (Cypress processor)) for reconfiguration.

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