A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs

Kim, Hyeon‐June; Hwang, Sun-Il; Kwon, Ji-Wook; Jin, Dayong; Choi, Byung-Soo; Lee, Sanggwon; Park, Jong-Ho; Shin, Jang−Kyoo; Ryu, Seung‐Tak

doi:10.1109/jssc.2016.2581819

Cited by 50 publications

(13 citation statements)

References 22 publications

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“…In order to reduce the FPN of the prototype APD, the off-chip digital offset adjustment was performed as in Refs. [20,21] so that the variation of APD can be reduced from 3.9 % to less than 0.1 % as shown in Figure 16. However, as the InGaAs APD was implemented as 16 partitioned cells in the prototype chip, the variation of APD is larger than the conventional one inducing the fixed pattern noise (FPN) [19], as shown in Figure 15a,b).…”

Section: Measurement Resultsmentioning

confidence: 97%

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High Spatial Resolution Three-Dimensional Imaging Static Unitary Detector-Based Laser Detection and Ranging Sensor

et al. 2019

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This paper presents a static unitary detector (STUD)-based laser detection and ranging (LADAR) sensor with a 16-to-1 transimpedance-combining amplifier for high spatial resolution three-dimensional (3-D) applications. In order to readout the large size of a photodetector for better results of 3-D information without any reduction of the bandwidth, the partitioning photosensitive cell method is embedded in a 16-to-1 transimpedance-combining amplifier. The effective number of partitioning photosensitive cells and signal-combining stages are selected based on the analysis of the partitioning photosensitive cell method for the optimum performance of a transimpedance-combining amplifier. A prototype chip is fabricated in a 0.18-μm CMOS technology. The input referred noise is 41.9 pA/√Hz with a bandwidth of 230 MHz and a transimpedance gain of 70.4 dB·Ω. The total power consumption of the prototype chip is approximately 86 mW from a 1.8-V supply, and the TICA consumes approximately 15.4 mW of it.

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Section: Measurement Resultsmentioning

confidence: 97%

Section: Measurement Resultsmentioning

confidence: 97%

High Spatial Resolution Three-Dimensional Imaging Static Unitary Detector-Based Laser Detection and Ranging Sensor

et al. 2019

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“…This made it difficult to clarify the distinct range information. In order to reduce the pixel FPN of the prototype APD, off-chip digital offset adjustment was performed as off-chip calibration as in [17,23], so that the offset difference between neighboring pixels could be reduced to under 1 LSB. After offset adjustment, the pixel FPN was reduced to less than 0.1%.…”

Section: Measurement Results and Discussionmentioning

confidence: 99%

“…It could result in the loss of echo information (second echo and third echo) within T DR even though the first echo had already been detected at the Ø SP[n] . In the case of the serial data readout structure as in [15,16,17], the wasted time (T DR ) increases if the pixel resolution is increased and makes it difficult to successively detect incoming echoes, resulting in the deterioration of the detection latency of the FPA-based LADAR system. Here, the detection latency means the total time to become ready to receive the next incoming echo after the previous echo detection.…”

Section: Proposed Readout Schemementioning

confidence: 99%

A High-Multi Target Resolution Focal Plane Array-Based Laser Detection and Ranging Sensor

Kim

Lee

Kim

2019

Sensors

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This paper introduces a digital-assisted multiple echo detection scheme, which utilizes the waste time of the full serial data readout period in a focal plane array (FPA)-based laser detection and ranging (LADAR) receiver. With the support of an external digital signal processor (DSP) and additional analog memory inserted into the receiver, the proposed readout scheme can effectively enhance multi-target resolution (MTR) three times higher than the conventional FPA-based LADAR, while maintaining low power consumption and a small area. A prototype chip was fabricated in a 0.18-μm CMOS process with an 8 × 8 FPA configuration, where each single receiver pixel occupied an area of 100 μm × 100 μm. The single receiver achieved an MTR of 20 ns with 7.47 mW power dissipation, an input referred noise current of 4.48 pA/√Hz with a bandwidth 530 MHz, a minimum detectable signal (MDS) of 340 nA, a maximum walk error of 2.2 ns, and a maximum non-linearity of 0.05% among the captured multiple echo images.

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“…The bit of the edge detector is determined according to the edge threshold. The difference between adjacent pixels that exceed the 15 least significant bits (LSB) out of 256 full-scale codes is less than 10% of the entire image, and this value decreases as the image resolution increases [ 27 ]. Therefore, if the difference is more than 8 LSB in the image, the change could be considered sufficiently sudden, and the region could be processed as an edge in the image.…”

Section: Design Of the Proposed Edge-detection Cmos Image Sensormentioning

confidence: 99%

Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits

Jin¹,

Noh²,

Song³

et al. 2020

Sensors

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In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

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A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs

Cited by 50 publications

References 22 publications

High Spatial Resolution Three-Dimensional Imaging Static Unitary Detector-Based Laser Detection and Ranging Sensor

High Spatial Resolution Three-Dimensional Imaging Static Unitary Detector-Based Laser Detection and Ranging Sensor

A High-Multi Target Resolution Focal Plane Array-Based Laser Detection and Ranging Sensor

Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits

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