A Dependability Solution for Homogeneous MPSoCs

Abstract

Nowadays highly dependable electronic devices are demanded by many safety-critical applications. Dependability attributes such as reliability and availability/maintainability of a many-processor system-on-chip (MPSoC) should already be examined at the design phase. Design for dependability approaches such as using available fault-free processor-cores and introducing a dependability manager infrastructural IP for selftest and evaluation can greatly enhance the dependability of an MPSoC. This is further supported by subsequent software-based repair. Design choices such as test fault coverage, test and repair time are examined to optimize the dependability attributes. Utilizing existing infrastructures like a network-on-chip (NoC) and tile-wrappers are needed to ensure a test can be performed at application run-time. An example design following the proposed design for dependability approach is shown. The MPSoC has been processed and measurement results have validated the proposed dependability approach.

Linking aging measurements of health-monitors and specifications for multi-processor SoCs

“…To counteract this loss, use can be made of multi-processors. Our generic approach for implementing high-dependability SoCs uses onchip health monitor tests or measurements on processor cores during their operational life to evaluate their health and subsequent repair of (to be) faulty processors by remapping and rerouting (spare) correct cores using run-time mapping software [3,4,5]. Combining health monitors and prognostics in electronics as such has been suggested before [6].…”

“…In earlier work, e.g. paper [3], the processor cores were structurally tested via scan chains during their life time. This has the disadvantage that during those tests, the processor cores have to be isolated (nonoperational) to be tested; furthermore, reactive repair via remapping is performed only after fault detection via testing.…”

“…Our prognostic approach for life-time prediction of cores uses on-chip health monitors (e.g. supply-voltage monitoring) per core in combination with advanced prediction algorithms in software to ensure a high dependability, using the same repair mechanisms as before [3]. However, this approach assumes that there is a close correlation between the on-chip HM measurements and key core specification parameters, like e.g.…”

Reliability-Driven Task Mapping for Lifetime Extension of Networks-on-Chip Based Multiprocessor Systems

“…This was later extended for MTTF evaluation of an MPSoC employing multiple cores [8]. A parallel research direction is to optimize system MTTF at the application mapping phase assuming constant failure rate for cores [9]. Wear-out related effects are not incorporated in the analysis leading to inaccuracies in lifetime computation and optimization.…”