A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond

Abstract

Abstract. The Sandia National Laboratories (SNL) Data Encryption Standard (DES) Application Specific Integrated Circuit (ASIC) is the fastest known implementation of the DES algorithm as defined in the Federal Information Processing Standards (FIPS) Publication 46-2. DES is used for protecting data by cryptographic means. The SNL DES ASIC, over 10 times faster than other currently available DES chips, is a high-speed, fully pipelined implementation offering encryption, decryption, unique key input, or algorithm bypassing on each clock cycle. Operating beyond 105 MHz on 64 bit words, this device is capable of data throughputs greater than 6.7 Billion bits per second (tester limited). Simulations predict proper operation up to 9.28 Billion bits per second. In low frequency, low data rate applications, the ASIC consumes less that one milliwatt of power. The device has features for passing control signals synchronized to throughput data. Three SNL DES ASICs may be easily cascaded to provide the much greater security of triple-key, triple-DES.

Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security

“…IDEA architecture uses a modified transformation round, which minimizes the allocated area resources by about 30%, compared with other works [7,36,48]. DES proposed implementation performs better, with a range from 200 to 400%, compared with the other related works [5,13,21,44]. Especially, the proposed DES architecture has been designed with a slight modification, in order to operate alternatively as an Authorized User Verification Unit.…”

“…The total key schedule process was analyzed and according to our study is proved that a certain combinational shift register can produce every round key. The key Expansion Unit design in the proposed DES architecture is built on 16 different shift registers and not with a full rolling design technique, used in previous published works [5,13,21,44]. With this applied technique (shift registers), DES performance is increased at about 170% compared with any architecture with a key expansion unit, built on the defined key scheduling logical components [5,13,21,44].…”

Biomedical Image Transmission Based on Modified Feistal Algorithm

“…VLSI implementation of DES on static 0.6 micron CMOS technology [7] is the fastest implementation of DES reported by the literature. The image encryption scheme was implemented in design with skew and also without skew core key scheduling and the device utilization details are shown in figure. And it is found that pipelined DES has high speed, high data throughput and less CLB utilization.…”

FPGA based Secure Biomedical Image Transmission

“…A VLSI implementation of DES on static 0.6 micron CMOS technology at [7] is the fastest implementation of DES reported in the literature. The image encryption scheme was implemented in design with skew and also without skew core key scheduling and the device utilization details are shown in figure. And it is found that pipelined DES has high speed, high data throughput and less CLB utilization.…”