A design assembly framework for FPGA back-end acceleration

Frangieh, T.; Athanas, Peter

doi:10.1016/j.micpro.2014.02.008

Cited by 9 publications

(7 citation statements)

References 22 publications

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“…Xilinx Hierarchical Design Partitions flow [49] and qFlow [16]. Both are incremental, partial implementation frameworks that reduce build times through high-level management of the Xilinx ISE implementation process.…”

Section: Incremental Compilationmentioning

confidence: 99%

“…This second utilizes a subset of the qFlow framework [16], a tool for accelerating back-end compilation of designs with hierarchical structure similar to that enforced by the Convey PDK. Though qFlow offers a superset of the functionality provided by Partitions, the application discussed here is similar.…”

Section: Qflowmentioning

confidence: 99%

“…This section covers the results of reducing the compilation times in the bFlow framework using the Xilinx Partitions flow [49] and the qFlow framework [16]. Due to time constraints, these techniques were not applied to the bitstream compilation phase in ConVI.…”

Section: Compilation Performancementioning

confidence: 99%

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FPGA-based accelerator development for non-engineers

Uliana

Athanas

Kȩpa

2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

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In today's world of big-data computing, access to massive, complex data sets has reached an unprecedented level, and the task of intelligently processing such data into useful information has become a growing concern to the high-performance computing community. However, domain experts, who are the brains behind this processing, typically lack the skills required to build FPGA-based hardware accelerators ideal for their applications, as traditional development flows targeting such hardware require digital design expertise. This work proposes a usable, end-to-end accelerator development methodology that attempts to bridge this gap between domain-experts and the vast computational capacity of FPGA-based heterogeneous platforms. To accomplish this, two development flows were assembled, both targeting the Convey Hybrid-Core HC-1 heterogeneous platform and utilizing existing graphical design environments for design entry. Furthermore, incremental implementation techniques were applied to one of the flows to accelerate bitstream compilation, improving design productivity. The efficacy of these flows in extending FPGA-based acceleration to non-engineers in the life sciences was informally tested at two separate instances of an NSF-funded summer workshop, organized and hosted by the Virginia Bioinformatics Institute at Virginia Tech.In both workshops, groups of four or five non-engineer participants made significant modifications to a bare-bones Smith-Waterman accelerator, extending functionality and improving performance.

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Section: Incremental Compilationmentioning

confidence: 99%

Section: Qflowmentioning

confidence: 99%

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FPGA-based accelerator development for non-engineers

Uliana

Athanas

Kȩpa

2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

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“…Traditional Simulated Annealing (SA) based placement algorithms are known to produce superior quality placement results for small and medium scale designs. However, SA does not scale well for larger designs, and hence resulting in longer runtime [9].…”

Section: Introductionmentioning

confidence: 99%

Performance Estimation of FPGA Modules for Modular Design Methodology Using Artificial Neural Network

Herath

Prakash

Srikanthan

2018

Applied Reconfigurable Computing. Architectures, Tools, and Applications

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Modern FPGAs consist of millions of logic resources allowing hardware designers to map increasingly large designs. However, the design productivity of mapping large designs is greatly affected by the long runtime of FPGA CAD flow. To mitigate it, modular design methodology has been introduced in the past that allows designers to partition large designs into smaller modules and compile & test the modules individually before assembling them together to complete the compilation process. Automated decision making on placing these modules on FPGA, however, is a slow and tedious process that requires large database of precompiled modules, which are compiled on a large number of placement positions. To accelerate this placement process during modular designing, in this paper we propose an ANN based performance estimation technique that can rapidly suggest the best shape and location for a given module. Experimental results on legacy as well as state-of-the-art FPGA devices show that the proposed technique can accurately estimate the F max of modules with an average error of less than 4%.

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“…BPR [7], on the other hand, creates modules with much bigger components such as FFT and FIR Filters. Module creation in QFlow [120] is based on the rate of modifications required in each module creating invariant and evolving sets rather than ones based on granularity. However, all these techniques focus on faster CAD flow runtime, but do not consider performance or power.…”

Section: Module Creationmentioning

confidence: 99%

Mapping large-scale systems on to high density FPGAs

Herath¹

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First and foremost, I would like to express my heartfelt gratitude to my supervisor and mentor, Prof. Thambipillai Srikanthan, for his valuable guidance, motivation, and support for a successful and uninterrupted Ph.D. journey. Without his dedication in my research project, this Ph.D. would never be a reality. It was a complete privilege to have not only his expertise in the research domain, but also his valuable pieces of advice given as a beautiful human spirit. My warmest gratitude also goes to Dr. Alok Prakash. His enormous support and dedication throughout this research is invaluable. Brainstorming and in-depth technical discussions along with his thorough revision of research writings helped me to produce back to back publications. His assistance to me was always one step ahead of my expectations, and this gratitude will never be enough. I would also like to thank Dr. Lam Siew Kei for strengthening the research topic in the early stages. It is also impossible to forget the support given by Dr. Guiyuan in my research. My sincere appreciation also goes to Dr. Ravi Kumar Satzoda for nourishing my interests in FPGAs towards a Ph.D. I would thankfully like to remind the administrative support of Mr. Jeremiah Chua and Ms. Poh Ling. Mr. Jeremiah's swift responses in technical difficulties I encountered were always helpful. Ms. Poh Ling has always been a strength to me in policies and formalities, especially during candidature extension process when I did not see any hope. I would also like to pay my warmest appreciation for all the beautiful people in NTU canteens who always made me smile with an extra bit of food and care. I was very fortunate to have my friend, Mr. Aung Lwin Phyo beside me during the time got tough in all aspects. His warmest support assisted me in focusing on my research without any worry. His financial support during the confirmation examination is one of the best things I have ever got from a friend. My colleagues, Deshya, and Thilina, has always given their touching support to me throughout my research. Lunch breaks, coffee times with them, and xiv of course, their home-cooked treats has helped me to leave heavy minds behind. I always knew that I could count on them. My colleagues Vijeta and Supriya were sisters to me, who always approached me with the most exceptional help. My confirmation examination could not be a success without them. Max Wang's support during the last mile in this Ph.D. has comforted me to stay on track when nothing seemed to be in my favor. Thank you, all. My family has always been the greatest strength to me. Though my father is not around with me today, he has ensured I grow up this far without any hassle. My mother has given the love of both parents since my father's passing, that I found the worth in this tough journey. My two sisters, my brother, and my brother-in-law, were always my best friends that anyone can envy. Their support in this research was always silent and often disguised as a box of rice, a dessert, a car ride, or even as hidden beautiful gifts. But...

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A design assembly framework for FPGA back-end acceleration

Cited by 9 publications

References 22 publications

FPGA-based accelerator development for non-engineers

FPGA-based accelerator development for non-engineers

Performance Estimation of FPGA Modules for Modular Design Methodology Using Artificial Neural Network

Mapping large-scale systems on to high density FPGAs

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