A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification

Abstract-This paper introduces adaptive techniques targeted for heterogeneous manycore architectures and introduces the FlexTiles platform, which consists of general purpose processors with some dedicated accelerators. The different components are based on low power DSP cores and an eFPGA on which dedicated IPs can be dynamically configured at run-time. These features enable a breakthrough in term of computing performance while improving the on-line adaptive capabilities brought from smart heuristics. Thus, we propose a virtualisation layer which provides a higher abstraction level to mask the underlying heterogeneity present in such architectures. Given the large variety of possible use cases that these platforms must support and the resulting workload variability, offline approaches are no longer sufficient because they do not allow coping with time changing workloads. The upcoming generation of applications include smart cameras, drones, and cognitive radio. In order to facilitate the architecture adaptation under different scenarios, we propose a programming model that considers both static and dynamic behaviors. This is associated with self adaptive strategies endowed by an operating system kernel that provides a set of functions that guarantee quality of service (QoS) by implementing runtime adaptive policies. Dynamic adaptation will be mainly used to reduce both overall power consumption and temperature and to ease the problem of decreasing yield and reliability that results from submicron CMOS scales.

show abstract

“…The SDF3 tools [19] and the AEthereal tools [20] are used for this. NoC connections can also be computed at run time [21].…”

Section: H Software Toolsmentioning

confidence: 99%

Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures

Lemonnier

Millet

Almeida

et al. 2012

2012 International Conference on Embedded Computer Systems (SAMOS)

View full text Add to dashboard Cite

show abstract

“…Another framework is presented by Kogel [11]. In the design flows of AEthereal [7] and xpipesCompiler [8], SystemC simulation is used for performance validation.…”

Section: Related Workmentioning

confidence: 99%

Using an FPGA for Fast Bit Accurate SoC Simulation

Wolkotte

Hölzenspies

Smit

2007

2007 IEEE International Parallel and Distributed Processing Symposium

View full text Add to dashboard Cite

show abstract

“…They provide attractive characteristics mainly energy efficiency and reliability [7] . They also supply scalable bandwidth when compared to traditional bus architectures [16,21] End to end communication in a system is accomplished by the exchange of messages among IP cores. Often, the structure of particular messages is not adequate for communication purposes.…”

Section: Introductionmentioning

confidence: 99%

“…As described in [10,11,15,16] , NoCs are emerging as the best solution to the existing interconnection architecture constraints. They provide attractive characteristics mainly energy efficiency and reliability [7] .…”

Section: Introductionmentioning

confidence: 99%

Study of Network on Chip resources allocation for QoS Management

Helali¹,

Soudani²,

Bhar³

et al. 2006

J. of Computer Science

View full text Add to dashboard Cite

Abstract:The increasing complexity of integrated circuits and application requirements drive the research of new on-chip interconnection architectures. A network on chip draws on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. The main goal pursued is to achieve superior bandwidth when compared to conventional onchip bus architectures. The complexity of Systems-on-Chip (SoC) is growing; meeting real-time requirements is becoming increasingly difficult. Predictability for computation, memory and communication components are needed to build up real-time SoC. To achieve guaranteed throughput and bounded delivery delay, buffers in network interfaces (NIs) must be dimensioned to hide round-trip latency and rate difference between computation and IPs communication.. It is crucial to shape these buffers according to the network requirements and to bring out the right specification before the design step to provide desired performances in the SoC. In this field this paper describes and presents a performance analyses of NoC shaped on mesh architecture. The goal of this work is to quantify buffering requirements in the NoC nodes by the analyze of some QoS metrics such as drop, compute latency, and throughput. This study presented in this paper is based on simulation approach of a mesh (4 x 4 ) NoC behavior under multimedia communication process with MPEG-4 (Moving Picture Experts Group) flows.

show abstract

A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification

Cited by 143 publications

References 15 publications

Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures

Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures

Using an FPGA for Fast Bit Accurate SoC Simulation

Study of Network on Chip resources allocation for QoS Management

Contact Info

Product

Resources

About