A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors

Karuri, Kingshuk; Chattopadhyay, Anupam; Chen, Xiaolin; Kammler, David W.; Hao, Ling; Leupers, Rainer; Meyr, H.; Ascheid, Gerd

doi:10.1109/tvlsi.2008.2002685

Cited by 35 publications

(24 citation statements)

References 30 publications

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“…Sistla, K. Patel and G. Mehta / Human Computation (2015) 2:1 2000b; Karuri et al, 2008;Bauer et al, 2009)). This research is complementary to our own and can contribute to better tools for architectural exploration.…”

Section: Cross-architectural Studiesmentioning

confidence: 99%

“…Good tools are needed to allow designers to identify efficient architectures for an application domain. Some of these design space exploration tools have already been developed, laying groundwork for progress in this direction (e.g., (Hartenstein et al, 2000b), (Karuri et al, 2008), (Bauer et al, 2009), (Kim et al, 2010)). However, one bottleneck for any of these tools is that it can be time consuming and difficult to properly evaluate a proposed architecture, especially if that architecture is quite novel or highly customized.…”

Section: Introductionmentioning

confidence: 99%

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Crowdsourcing the mapping problem for design space exploration of custom reconfigurable architecture designs

Sistla¹,

Patel²,

Mehta³

2015

HCj

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One of the grand challenges in the design of portable/wearable electronics is to achieve optimal efficiency and flexibility in a tiny low power package. Coarse grained reconfigurable architectures (CGRAs) hold great promise for low power, high performance, and flexible designs for a domain of applications. CGRAs are very promising due to the ability to highly customize such architectures to an application domain. However, greater customization makes the mapping of applications onto these architectures very challenging. Good tools and fast, effective mapping algorithms are needed to support design space exploration for CGRAs. In particular, the mapping problem has been difficult to solve in a satisfying and general way. In this paper, we present an architectural design flow using crowdsourcing to provide mappings of benchmarks onto new architectures. We show that the crowd can provide high quality, reliable mappings, significantly outperforming our custom Simulated Annealing algorithm in almost all cases. We further show that the crowd can provide other types of feedback that are difficult to obtain from an automatic mapping algorithm. Our proof of concept cross-architectural study supports an 8Way or 4Way1Hop architecture as a top choice, concludes that a custom modification that constrains inputs and outputs consumes less energy but requires more area than its less constrained counterpart, and suggests that Stripe architectures are interesting to consider because they perform nearly as well as our mesh variants and may present a more straightforward mapping problem for the crowd or an automatic mapping algorithm.

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Section: Cross-architectural Studiesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Crowdsourcing the mapping problem for design space exploration of custom reconfigurable architecture designs

Sistla¹,

Patel²,

Mehta³

2015

HCj

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“…As can be seen from Figure 1, a rASIP architecture consists of three components namely, the base processor, the ASIP-FPGA coupling and the FPGA architecture [3]. These three components can be designed using numerous design alternatives.…”

Section: Fig 1: Rasip Architecturementioning

confidence: 99%

“…A generic rASIP for private key cryptographic applications has been proposed [3] in which fast SRAM based scratch pad was added to reconfigurable block to speed up the application execution.…”

Section: Related Workmentioning

confidence: 99%

A Survey of Reconfigurable Architectures

PratapSingh¹,

Jain²

2014

IJCA

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A new architecture type that is recently evolving is the reconfigurable architecture which combines the benefits of ASIPs (Application Specific Instruction Set Processors) and FPGAs (Field Programmable Gate Arrays). Reconfigurable computing combines software flexibility with high performance hardware. FPGAs are generally employed to construct a reconfigurable block as it provides an instant timeto-market advantage. Reconfigurable devices like FPGA offers improved computational efficiency as compared to traditional processor architectures. Reconfigurable block in these architectures provides the required flexibility for a large variety of embedded applications. Design space exploration of reconfigurable block involves a wide range of alternatives like logic block granularity in FPGA, interconnect topology, etc. The goal of this paper is to explore the reconfigurable architectures.

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“…With the requirements for higher performance and flexibility in embedded design, reconfigurable computing [1,2,3] is becoming more promising than application specific integrated circuit (ASIC) and digital signal processor (DSP). Reconfigurable architectures have been proposed as a compromise approach as they are flexible, scalable and can provide reasonable computing capability.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of high performance matrix inversion based on reconfigurable processor

Wang

Feng

et al. 2016

IEICE Electron. Express

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In this paper, we propose a high performance matrix inversion implementation on a reconfigurable application specific processor. Our implementation can accelerate variable order matrix inversion ranging from 4 to 144. We adopt LU decomposition to reduce the computation complexity and a pivoting operation to ensure the stability. In order to get higher performance within the limited resources, parallel computing and timesharing multiplexing are employed. The chip testing results show that our implementation improve the performance of inversion efficiently. The highest parallel speed-up ratio can achieve 3 times, and the execution time of a 144 × 144 matrix inversion is 4.07 ms.

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A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors

Cited by 35 publications

References 30 publications

Crowdsourcing the mapping problem for design space exploration of custom reconfigurable architecture designs

Crowdsourcing the mapping problem for design space exploration of custom reconfigurable architecture designs

A Survey of Reconfigurable Architectures

Design and implementation of high performance matrix inversion based on reconfigurable processor

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