A Design Flow for Click-Based Asynchronous Circuits Design With Conventional EDA Tools

Abstract

The "event-driven" feature of asynchronous circuits enables the circuits to work when and where needed, making it a good alternative to design low-power circuits. However, asynchronous circuits are not widely adopted as a consequence of the lack of support by conventional EDA tools. In this paper, we propose a novel design flow to implement the Click-based asynchronous bundled-data circuits efficiently down to mask layout with conventional EDA tools. To ensure timing correctness, we put forward an adaptive delay matching (ADM) method and perform accurate static timing analysis for the circuits. Compared with other asynchronous toolsets, the proposed design flow is more efficient and convenient to implement asynchronous circuits. An asynchronous convolution neural network accelerator is implemented in TSMC 180nm and 65nm CMOS process respectively to verify the proposed design flow. The silicon test results show that the asynchronous accelerator has 30% less power in computing array than the synchronous one in TSMC 65nm CMOS process, and the energy efficiency of the asynchronous and synchronous accelerators are 1.539 TOPS/W and 1.37 TOPS/W respectively. The energy efficiency of the asynchronous accelerator in TSMC 180nm CMOS process is 133 GOPS/W.

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