A design flow for partially reconfigurable hardware

Abstract

This paper presents a top-down designer-driven design flow for creating hardware that exploits partial run-time reconfiguration. Computer-aided design (CAD) tools are presented, which complement conventional FPGA design environments to enable the specification, simulation (both functional and timing), synthesis, automatic placement and routing, partial configuration generation and control of partially reconfigurable designs. Collectively these tools constitute the dynamic circuit switching CAD framework. A partially reconfigurable Viterbi decoder design is presented to demonstrate the design flow and illustrate possible power consumption reductions and performance improvements through the exploitation of partial reconfiguration

OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems

“…The toolset then generates a simulation model for debugging. Since the design is already given in VHDL, FPGA vendor tools are used to implement the design [14].…”

Customized kernel execution on reconfigurable hardware for embedded applications

“…Numerous embedded applications spend substantial time on a few software kernels [1]. Executing these kernels on customized hardware could reduce the execution time and energy consumption as compared to software realizations [2,3]. Given reconfigurable hardware, such as FPGAs, a chosen area could accommodate exclusively such kernels at different times to conserve resources, thus saving space and possibly power.…”

Resource management for dynamically-challenged reconfigurable systems

“…Numerous embedded applications spend substantial execution time on a few software kernels [1]. Executing these kernels on customized hardware tailored to their requirements could reduce the overall execution time and energy consumption as compared to implementing them with software [2]. Moreover, multiple kernels rarely appear simultaneously during execution of the application.…”

“…Moreover, reconfigurable hardware can ensure reusability of a given chip-area by many embedded operations, thus saving space and possibly power. For example, a Viterbi decoder can use the same hardware configured differently to implement several decoding schemes based on various channel conditions [2]. An important feature of current FPGA architectures is their support of reconfiguration for portion of the FPGA while the remainder of the design is still in operation.…”

“…Reconfigurable hardware can provide these benefits at a higher execution speed than respective software. Many dynamically reconfigurable systems (both embedded and non-embedded) involve a host processor [2,3,9,10,11]. The host is mainly used for control oriented, less computation intensive tasks.…”