A Design Method for Nested MASH-SQ Hybrid Divider Controllers for Fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math> </inline-formula> Frequency Synthesizers

Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers

“…The phase deviation caused by the divider controller is related to its accumulated quantization error in the analytical model for a fractional-N frequency synthesizer [2]. The accumulated quantization error of a MASH-SR can be expressed as [15] t…”

“…Notice that the contribution of the accumulated quantization error from the MASH DDSM part is scaled by a factor 1/M 1 . As a result, the accumulated quantization error from the SR typically dominates the spectral performance [15]. To achieve a t[n] spectrum that is similar to that of a full SR implementing the same pair of state transition matrices, it is required that the order of the MASH DDSM be greater than or equal to that of the SR [15].…”

“…As a result, the accumulated quantization error from the SR typically dominates the spectral performance [15]. To achieve a t[n] spectrum that is similar to that of a full SR implementing the same pair of state transition matrices, it is required that the order of the MASH DDSM be greater than or equal to that of the SR [15]. As simulations suggest, with a sufficient number of quantization blocks, the MASH-SR can achieve a similar effect in terms of the suppression of fixed spurs induced by the divider controller, when compared with a MASH DDSM divider controller [15].…”

“…The MASH-SR is a hybrid between these two classes of divider controllers. It has a nested-cascaded structure that consists of a MASH DDSM and cascaded quantization blocks [14], [15], [16], [17]. The input to the divider controller is partitioned and quantized by a MASH and a SR. Consequently, fewer quantization blocks are needed to perform the quantization of the divider controller input.…”

“…The input to the divider controller is partitioned and quantized by a MASH and a SR. Consequently, fewer quantization blocks are needed to perform the quantization of the divider controller input. Due to the dominance of the phase noise contribution from the SR stages that quantize the most significant bits (MSBs) and the output of the MASH DDSM, the performance of the MASH-SR, both in terms of spur immunity and noise contribution, is close to that of the full-length cascaded SR [14], [15]. Similar to the SR, a MASH-SR can be optimized by choosing the state transition matrices.…”