A design methodology for synthesizing parallel algorithms and architectures

Chen, Marina C.

doi:10.1016/0743-7315(86)90010-9

Cited by 85 publications

(14 citation statements)

References 2 publications

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“…Our findings imply that (k − 1) n−1 node-disjoint cycles can be emulated in G k,n . Previously, a number of parallel algorithms that can be executed on cycles have been developed [6]. Those algorithms can also be executed on G k,n .…”

Section: Discussionmentioning

confidence: 99%

The k‐degree Cayley graph and its topological properties

Hsieh

Hsiao

2005

Networks

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This article introduces a new family of Cayley graphs, called k -degree Cayley graphs, for building interconnection networks. The k -degree Cayley graph possesses many valuable topological properties, such as regularity with degree k , logarithmic diameter, and maximal fault tolerance. We present an optimal shortest path routing algorithm for the k -degree Cayley graph. Cycleembedding and clique-embedding are also discussed.

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Section: Discussionmentioning

confidence: 99%

The k‐degree Cayley graph and its topological properties

Hsieh

Hsiao

2005

Networks

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“…A lot of research has been devoted to systematically synthesise systolic arrays from an algorithm description [2]- [8]. The basic idea is to apply a space-time mapping (transformation) to the algorithm so that the transformed algorithm represents a systolic array.…”

Section: Introductionmentioning

confidence: 99%

Closed-form mapping conditions for the synthesis of linear processor arrays

Xue

1995

Journal of VLSI Signal Processing

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Abstract. This paper addresses the problem of mapping algorithms with constant data dependences to linear processor arrays. The closed-form necessary and sufficient mapping conditions are derived to identify mappings without computational conflicts and data link collisions. These mapping conditions depend on the space-time mapping matrix and the problem size parameters only. Their correctness can be verified in constant time that is independent of problem size. The design of optimal linear processor arrays is formulated as a mathematic programming problem, which can be solved efficiently by a systematic enumeration of a polynomial search space.

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“…For simplicity, we assume 3b divides d henceforth. 4 Next, we will prove a result on one-many routing with the restriction that all type-i packets reside in type-i terminals initially. Then we will describe how to perform onemany routing without this restriction.…”

Section: Routing On Two-dimensional Short-bus Meshesmentioning

confidence: 99%

“…Routing with locality problems arises naturally when specific known algorithms are implemented on the mesh [13] and when other types of processor or process networks are embedded onto mesh-connected computers to yield a small dilation. In fact, one of the goals in designing parallel algorithms is to try to make distances between related processes as short as possible [4]. If the maximum distance of all the time steps lower bound proof for the permutation routing problem on meshes with fixed buses [17].…”

Section: Introductionmentioning

confidence: 99%

Routing with Locality on Meshes with Buses

Cheung

Lau

1996

Journal of Parallel and Distributed Computing

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packets is bounded by d, the authors have presented in [6] a d ϩ O(d/f (d)) step, O( f (d)) buffer size routing algorithm which is asymptotically optimal if f (d) is chosen to be a large constant. In our study, we assume all the processors operate in synchronous MIMD mode. At any time step, each processor can communicate with all of its grid neighbors and can both send and receive one packet along each mesh link. In addition, processors can also store packets in their own queues. This model (hereafter referred to as the base model) is the same as the ones used in [9, 10, 12-16, 22, 25].The main disadvantage of the mesh topology is its large diameter, which has direct impact on the communication times of many parallel algorithms. Augmenting arrays of processors with various faster mechanisms has been suggested as a means to speed up communication among the processors. Examples are meshes with multiple buses which have a bus in each column and each row [1,20], generalized meshes with multiple buses which are composed of smaller meshes with multiple buses [8], meshes with separable row and column buses in which row/column buses can be separated into multiple shorter buses through turning on/off bus switches [24], and reconfigurable meshes in which links can be connected to form buses [2]. These enhanced meshes are capable of solving problems that only require a limited amount of global communication significantly faster. This paper shows how to utilize these buses in some ''high-bandwidth'' routing problems.In all the related bused mesh models, except reconfigurable meshes, broadcast buses are added to the base model. Each broadcast bus is connected to a set of processors. In each time step, only one processor attached to a bus can send a packet via the bus. In addition, a processor can receive packets from all the buses attached to it in a time step. A number of proposed bused mesh models assume the propagation delay of a bus to be a constant which is independent of the number of processors attached to it. This assumption is thought to be a reasonable one in practical situations [1,2,3,20,27]. However, Lu et al. [18] investigated physical implementations of buses and found that short buses and long buses do have a difference in performance and that the constant-delay assumption is more appropriate with short-bus models. In this paper, we assume the propagation delay of the buses to be one time step which is also assumed in [1,8,17,27]. As we will see, JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 33, 84-90 (1996) Routing with locality is studied for meshes with buses. In this problem, packets' distances are bounded by a value, d, which is less than the diameter of the network. This problem arises naturally when specific known algorithms are implemented on meshes. Solving this problem in ordinary meshes requires at least a routing time of d steps. To do better than this, we propose adding a kind of short bus to ordinary meshes. By using a technique which we call iterative walk-and-ride, we show how the routing ...

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A design methodology for synthesizing parallel algorithms and architectures

Cited by 85 publications

References 2 publications

The k‐degree Cayley graph and its topological properties

The k‐degree Cayley graph and its topological properties

Closed-form mapping conditions for the synthesis of linear processor arrays

Routing with Locality on Meshes with Buses

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