A Design of a Fast Parallel-Pipelined Implementation of AES: Advanced Encryption Standard

ElKabbany, Ghada F.; Aslan, Heba K.; Rasslan, Mohamed

doi:10.5121/ijcsit.2014.6603

Cited by 6 publications

(2 citation statements)

References 10 publications

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“…The design of the hybrid-redundancy architecture has a pipeline structure based on five stages, where each stage is a set of data processing elements connected in series, which are executed in parallel and filled with the same data blocks in a time-sliced manner for independently computing five results (assuming that these will be equal). In applications where multiprocessors or multi-channels are required—for example, in works developed by Elkabbany et al [ 42 ] and Nabil et al [ 43 ]—a pipeline architecture increases the performance and throughput by processing independent communications lines; in our case, the pipeline architecture is used for processing the same data block, focusing on the detection and correction of errors. For this process, some buffer storage (pipeline registers) is inserted between the five data processing elements, IR&F (Initial Round and Feedback), S&S (SubBytes and ShiftRows), M (Mix Columns), A (Add Round Key), and IC (Intermediate Cipher Data).…”

Section: Proposed Hardware Architecturementioning

confidence: 99%

Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES

Algredo‐Badillo

Ramírez-Gutiérrez

Morales-Rosales

et al. 2021

Sensors

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Currently, cryptographic algorithms are widely applied to communications systems to guarantee data security. For instance, in an emerging automotive environment where connectivity is a core part of autonomous and connected cars, it is essential to guarantee secure communications both inside and outside the vehicle. The AES algorithm has been widely applied to protect communications in onboard networks and outside the vehicle. Hardware implementations use techniques such as iterative, parallel, unrolled, and pipeline architectures. Nevertheless, the use of AES does not guarantee secure communication, because previous works have proved that implementations of secret key cryptosystems, such as AES, in hardware are sensitive to differential fault analysis. Moreover, it has been demonstrated that even a single fault during encryption or decryption could cause a large number of errors in encrypted or decrypted data. Although techniques such as iterative and parallel architectures have been explored for fault detection to protect AES encryption and decryption, it is necessary to explore other techniques such as pipelining. Furthermore, balancing a high throughput, reducing low power consumption, and using fewer hardware resources in the pipeline design are great challenges, and they are more difficult when considering fault detection and correction. In this research, we propose a novel hybrid pipeline hardware architecture focusing on error and fault detection for the AES cryptographic algorithm. The architecture is hybrid because it combines hardware and time redundancy through a pipeline structure, analyzing and balancing the critical path and distributing the processing elements within each stage. The main contribution is to present a pipeline structure for ciphering five times on the same data blocks, implementing a voting module to verify when an error occurs or when output has correct cipher data, optimizing the process, and using a decision tree to reduce the complexity of all combinations required for evaluating. The architecture is analyzed and implemented on several FPGA technologies, and it reports a throughput of 0.479 Gbps and an efficiency of 0.336 Mbps/LUT when a Virtex-7 is used.

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Section: Proposed Hardware Architecturementioning

confidence: 99%

Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES

Algredo‐Badillo

Ramírez-Gutiérrez

Morales-Rosales

et al. 2021

Sensors

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“…The optimal number of nodes to execute one modular multiplication is three. This level of parallelism enhances the ECC performance, since it solves the problem of load imbalance (Elkabbany et al, 2014). Then, to achieve load balancing, each ECPM operation can be computed by at most twelve nodes.…”

Section: Parallel Elliptic Curve Cryptographymentioning

confidence: 99%

Accelerating Digital Forensics through Parallel Computing

ElKabbany¹,

Rasslan²,

Aslan³

2018

Journal of Computer Science

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Digital crimes in the era of big data and cloud computing imposes significant challenges in digital forensics. Cloud environment provides low cost, easy management and reasonable solutions. Moreover, it supports big data structures and solutions (i.e., security, privacy and digital forensics). In order to achieve a secure digital forensics analysis in cloud environment, researchers have proposed solutions with expensive communication cost and computation overheads. Among these solutions Nasereldin et al. proposed a protocol which solves the problem of authenticity and integrity of evidence using signcryption technique. This leads to low communication and implementation overheads. Furthermore, identity-based cryptography is used to solve Public Key Infrastructure (PKI) problems. In addition, it is characterized by the ability to divide the message into small messages which is suitable for pipelining techniques. Nasreldin et al.'s signcryption protocol is based on Elliptic Curve Cryptography (ECC) which is implemented by using different mathematical operations. In this protocol, ECC mathematical operations take huge time during the execution of the algorithm. ECC consists of point doubling and point addition operations. These operations require the execution of many Montgomery modular multiplications that consume time. In this study, we introduce a technique to speed up ECC operations in order to enhance the efficiency of Nasreldin et al. protocol. In particular, we propose a multi-stage parallel design which consists of three stages. First, we speed up the point doubling and point addition operation. Secondly, we enhance the execution time of Montgomery multiplications. Finally, pipelining is used to obtain a better performance. The results show that the proposed design enhances Nasreldin et al. protocol's execution time by 47.1, 64.7, 73.5 and 79.4%, assuming that the number of nodes is 2, 4, 6 and 12, respectively.

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HiPAES: A Novel High Performance Parallel AES

Arun

Murali

Rajath

et al. 2020

2020 International Conference on Advanced Computer Science and Information Systems (ICACSIS)

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A Design of a Fast Parallel-Pipelined Implementation of AES: Advanced Encryption Standard

Abstract: The Advanced Encryption Standard (AES) algorithm is a symmetric block cipher which operates on a sequence of blocks each consists of 128, 192

Cited by 6 publications

References 10 publications

Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES

Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES

Accelerating Digital Forensics through Parallel Computing

HiPAES: A Novel High Performance Parallel AES

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