A design-oriented timing jitter/skew model in voltage-to-time converter (VTC) circuits

Mostafa, Hassan; Ismail, Yehea

doi:10.1007/s10470-014-0465-z

Cited by 4 publications

(3 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Timing jitter is a metric of how noise and process variations a®ect the produced VTC pulse delay in the time domain. 23 It generates a deviated pulse delay from the ideal one which limits the VTC design resolution. This deviated pulse error should be less than the time period that is corresponding to a LSB of the change in the applied analog input voltage signal.…”

Section: Jittermentioning

confidence: 99%

“…The calibration circuit integrated with the proposed design. The process variations main sources 23,24 at the 65 fnm CMOS technology, that a®ect the device parameters, are: (1) random dopants which are decreased in the MOSFET depletion region and results in variations of device threshold voltage (V TH ) which is proportional inversely to the square root of the transistor active area; and (2) channel length which impacts exponentially the V TH due to the Drain-Induced Barrier Lowering (DIBL) e®ect in short channel devices. These lead to variations on V TH or gate capacitance from the analog prospective and on gate delays or leakage currents from digital prospective.…”

Section: Process Variationsmentioning

confidence: 99%

See 1 more Smart Citation

A Novel MIM-Capacitor-Based 1-GS/s 14-bit Variation-Tolerant Fully-Differential Voltage-to-Time Converter (VTC) Circuit

El-Bayoumi

Mostafa

Soliman

2017

J CIRCUIT SYST COMP

Self Cite

View full text Add to dashboard Cite

Time-based Analog-to-Digital Converter (TADC), plays a major role in designing Software-Defined Radio (SDR) receivers, at scaled CMOS technologies, as it manifests lower area and power than conventional ADCs. TADC consists of 2 major blocks. The input voltage is converted into a pulse delay using a Voltage-to-Time Converter (VTC). In additions, the pulse delay is converted into a digital word using a Time-to-Digital Converter (TDC). In this paper, a novel fully-differential VTC based on a new methodology is presented which reports a highly-linear design. A metal-insulator-metal (MIM) capacitor as well as a dynamic calibration technique based on a set of large-sized capacitor-based voltage dividers circuits are utilized to automatically compensate the Process-Voltage-Temperature (PVT) variations. Moreover, the layout design is introduced. The proposed design operates on a 1[Formula: see text]GS/s sampling frequency with a supply voltage of 1.2[Formula: see text]V. After calibration, simulation results, using TSMC 65[Formula: see text]nm CMOS technology, report a 1.42[Formula: see text]V wider dynamic range due to the differential mechanism with a 3% linearity error. This design achieves a resolution up to 14 bits, a 0.07 fJ/conversion FOM, a 229[Formula: see text][Formula: see text]m2 area and a 0.25[Formula: see text]mW power. The simulation results are compared to the single-ended VTC results and the state-of-the-art analog-part ADCs results to show the strength of the proposed design.

show abstract

Section: Jittermentioning

confidence: 99%

Section: Process Variationsmentioning

confidence: 99%

A Novel MIM-Capacitor-Based 1-GS/s 14-bit Variation-Tolerant Fully-Differential Voltage-to-Time Converter (VTC) Circuit

El-Bayoumi

Mostafa

Soliman

2017

J CIRCUIT SYST COMP

Self Cite

View full text Add to dashboard Cite

show abstract

“…Band pass sampling for down conversion of a few RF signals is given in [14]. Timing jitter design model for Voltage-to-Time converter circuits is given in [15]. Design of asymmetrical resonator for microstrip triple-band and broadband band pass filters is presented in [16].…”

Section: Introductionmentioning

confidence: 99%

Universal Band Pass Sampling Algorithm for Integration of Multiple Wireless Technologies Using Software Defined Radio Platform

Budaraju¹,

Anjaneyulu²

2016

View full text Add to dashboard Cite

Software Defined Radio (SDR) architecture allows us to integrate different mobile technologies using common hardware but with different software modules. To achieve this, we need to keep the signal in digital form for as much portion of the circuitry as possible, so that the implementation could be carried out by programmable digital processors. For this purpose, the incoming radio frequency (RF) signal is down converted to baseband spectrum using band pass sampling method. Research works carried out so far in this field have developed a few algorithms for band pass sampling. But, these algorithms are not much useful for most of the mobile communication systems and they use complex methodology for computing the sampling frequency values. In order to use the SDR platform to integrate all current wireless technologies, an efficient, cost effective and less complex algorithm that can be labelled as universal band pass sampling algorithm is developed in this paper for multiple mobile systems. This algorithm is based on a novel idea of inserting guard bands between the signals which reduces the design complexities of perfect ADC and sharp cut off filters. Using this algorithm, valid sampling frequency ranges and corresponding IF values are calculated for down converting RF signals. The algorithm is tested for six RF signals of different wireless technologies which are integrated and simultaneously down converted using SDR based front end receiver and thus the system multiplies the base station capacity by a factor of six. The simulation results are obtained and shown in this paper which proves that the algorithm developed works well for most of the wireless technologies.

show abstract

Automated Current Mirror Layout (ACML) Tool

Atef¹,

Zaky

Ahmed

et al. 2019

2019 31st International Conference on Microelectronics (ICM)

View full text Add to dashboard Cite

A design-oriented timing jitter/skew model in voltage-to-time converter (VTC) circuits

Cited by 4 publications

References 16 publications

A Novel MIM-Capacitor-Based 1-GS/s 14-bit Variation-Tolerant Fully-Differential Voltage-to-Time Converter (VTC) Circuit

A Novel MIM-Capacitor-Based 1-GS/s 14-bit Variation-Tolerant Fully-Differential Voltage-to-Time Converter (VTC) Circuit

Universal Band Pass Sampling Algorithm for Integration of Multiple Wireless Technologies Using Software Defined Radio Platform

Automated Current Mirror Layout (ACML) Tool

Contact Info

Product

Resources

About