A design platform for 90-nm leakage reduction techniques

Abstract

Methodology, EDA Flow, scripts, and documentation plays a tremendous role in the deployment and standardization of advanced design techniques. In this paper we focus not only on leakage reduction techniques but also on their deployment as a worldwide infrastructure as the added-value resides not only in the techniques themselves but also in the way they are implemented to build an efficient, re-usable, robust, low cost and portable platform. Techniques have been silicon proven on the 90-nm TI CMOS technology and is commonly used to design SoC with complexities over 100 Million transistors LEAKAGE REDUCTION TECHNIQUESThe typical set of dynamic and leakage power reduction techniques we propose includes I ) idle (clock stopped), 2) standby (logic and memory retention with fast re-start using header and footer diodes), and 3) deep sleep (power off mode for ultra low power consumption using both voltage scaling and power gating) [I], DESIGN PLATFORMThe design platform that enables the integration of these techniques is the alliance of library cells and memory compilers, of EDA scripts and integration guidelines. Tools and Flow plays a tremendous role especially for verification. SpyglassTM rule checker at both RTL and gate level is efficient at catching errors such as "forgotten isolation cells". Other tools have been Copyright is held by the author/ovaer(s). DAC 2005, June I3-17,2005, Anaheim, California, USA. ACM 1 -59593-058-2/05/0006.developed to verify that the current surge that happens during the power restore sequence does not cause any issues.The complexity of SoC level leakage management can be handled by a divide-and-conquer approach. The SoC is split into several power managed IPS. We defined an IF as PM (Power Managed) if it can be put in retention or in off mode using, voltage scaling, power gating and Diode footed SRAM. We qualify an IP as being part at the PM framework if it is compliant with a set of rules for regularity (homogenous metal grid, embedded power switches on a regular pitch . . .) and present a standardized set of signals acting as a power control interface (similar to the 5 pins JTAG standard interface). Once a complete library of PM IPS (including CPU, DSP core, memories .. .) is available, SoC integrators can build up their design with the usual IP-based approach. From the physical point of view, each component can be placed according to regular metal grids. From the logic point of view, each power control interface will he plugged to a global "power controller". This dedicated block centralizes the power management and its scalable architecture allows it to open as many slots as required to plug all the PM IPS. Each slot contains small sequencers to generate autonomously the standard power down and wake up control sequences in sIave mode. All these sequencers are supervised and synchronized by the PWC (power controller). The PWC is always on and is controlled at software level where all the intelligent power management is actually happening. Figure 1: Die Microphotograph and Power Dom...