A Design Space Exploration Tool Set for Future 1K-core High-Performance Computers

Giorgi, Roberto; Procaccini, Marco; Khalili, Farnam

doi:10.1145/3300189.3300195

Cited by 7 publications

(9 citation statements)

References 30 publications

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“…Such models are described by using C/C++ (two orange blocks in the top left part of Figure 1). ese models are then embedded in the COTSon simulator, which is managed in turn by the MYDSE tools in order to perform the design space exploration [16,17,19]. e latter is a collection of different tools, which provide a fast and convenient environment to simulate, debug, optimize, and analyze the functional and timing models of a specific architecture and to select the candidate design to be migrated to the HLS (top part of Figure 1).…”

Section: Methodsmentioning

confidence: 99%

“…Moreover, COTSon permits building a complete distributed system with multi-cores and multiple nodes, where we can observe and analyze any aspect of the application and, e.g., the OS activity. In order to guarantee a proper scientific methodology for studying the experimental results that are coming from the framework, we designed a DSE toolset (called "MYDSE") [19], through which it is possible to easily set up a distributed simulation, as well as automatically extract, calculate the appropriate averages, and examine the key metrics. MYDSE addresses the designer's needs mostly on the first part of the workflow represented on the top of Figure 1.…”

Section: Simulatormentioning

confidence: 99%

“…In this subsection, we briefly summarize the features of the essential component of our toolchain-the COTSon-for the sake of a more self-contained illustration of our framework. More details can be found in [16,17,19,43].…”

Section: Simulatormentioning

confidence: 99%

“…In this subsection, we describe the tools that we have designed for the DSE. A detailed overview of these tools has been introduced in a previous work [19]. Here, we recall the main features.…”

Section: Dse Toolsetmentioning

confidence: 99%

“…Additionally, thanks to our DSE toolset (MYDSE) [17,19], we facilitate the extraction of not only important metrics such as the execution time but also more detailed ones such as cache miss rates and bus traffics, which help investigate the appropriate system design. In order to illustrate our methodology, we start from a driving example related to design a simple two-way associative cache system.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

Giorgi

Khalili

Procaccini

2019

International Journal of Reconfigurable Computing

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Translating a system requirement into a low-level representation (e.g., register transfer level or RTL) is the typical goal of the design of FPGA-based systems. However, the Design Space Exploration (DSE) needed to identify the final architecture may be time consuming, even when using high-level synthesis (HLS) tools. In this article, we illustrate our hybrid methodology, which uses a frontend for HLS so that the DSE is performed more rapidly by using a higher level abstraction, but without losing accuracy, thanks to the HP-Labs COTSon simulation infrastructure in combination with our DSE tools (MYDSE tools). In particular, this proposed methodology proved useful to achieve an appropriate design of a whole system in a shorter time than trying to design everything directly in HLS. Our motivating problem was to deploy a novel execution model called data-flow threads (DF-Threads) running on yet-to-be-designed hardware. For that goal, directly using the HLS was too premature in the design cycle. Therefore, a key point of our methodology consists in defining the first prototype in our simulation framework and gradually migrating the design into the Xilinx HLS after validating the key performance metrics of our novel system in the simulator. To explain this workflow, we first use a simple driving example consisting in the modelling of a two-way associative cache. Then, we explain how we generalized this methodology and describe the types of results that we were able to analyze in the AXIOM project, which helped us reduce the development time from months/weeks to days/hours.

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Section: Methodsmentioning

confidence: 99%

Section: Simulatormentioning

confidence: 99%

Section: Simulatormentioning

confidence: 99%

Section: Dse Toolsetmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

Giorgi

Khalili

Procaccini

2019

International Journal of Reconfigurable Computing

Self Cite

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DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model

Giorgi

Procaccini

Sahebi

2021

Architecture of Computing Systems

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A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors

Zaourar,

Chillet,

Philippe

2023

2023 26th Euromicro Conference on Digital System Design (DSD)

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High-performance many-core processors have complex computing architectures with many design parameters related to different levels (CPU macro/micro-architecture, interconnect, memory, specific accelerators, etc.). Design Space Exploration (DSE) is key to tackle the challenges related to the design of such processors, especially in the early stages. This work introduces A-DECA, a highly modular DSE approach for automating the exploration of design parameters. A-DECA combines simulators, models, and exploration strategies to derive relevant objective estimations while preserving a reasonable execution time. Thus, it provides a full methodology enabling the exploration of the design space in an easy-to-use, automatic, and effective way. A-DECA is evaluated in the context of next-generation HPC processors with various applications. We combine simulation tools and analytical formulations to assess PPA (Performance, Power, and Area). Based on an efficient implementation of a multi-objective genetic algorithm for the exploration strategy, current results show a great reduction of design space optimization by around 30% compared to the initial population. A-DECA optimizes the objectives and automatically returns a set of configurations with different characteristics allowing the architect to choose the best design according to the application context.

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A Design Space Exploration Tool Set for Future 1K-core High-Performance Computers

Cited by 7 publications

References 30 publications

Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model

A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors

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