A Detailed Model of the Switched-Resistor Technique

Abstract

The Switched-Resistor (S-R) approach is gaining popularity among integrated circuits designers because it allows to implement very high equivalent resistances, and thus very large time constants, in CMOS circuits. In this paper, we present an indepth analysis of the S-R technique and propose a novel detailed model which allows to accurately predict the value of the equivalent resistance even for values of the duty cycle as low as 0.0001% which result in a huge resistance multiplication factor. We show that the conventional model of the S-R technique provides a reasonable accuracy for duty cycle values down to 1%, but its accuracy becomes unacceptable for smaller values of the duty-cycle. In the proposed detailed model of the S-R we take into account also the parasitic capacitances of the integrated poly resistors and the non-ideal resistance of the CMOS switches. The modeling strategy is based on the solution of the differential equations for the different switches settings and exploits the Y-matrix to represents the floating S-R. The proposed model has been validated against periodic steady state (PSS) and periodic AC (PAC) simulations referring to a 130nm CMOS technology. Results have shown an average and maximum error lower than 0.53% and 5.15% respectively. As a further validation, a first-order active low-pass filter has been implemented with the same technology with a cutoff frequency tunable from 1.68Hz to 1.46kHz. The average and maximum error in the estimation of the cutoff frequency have resulted lower than 3.6% and 7% respectively.

A Detailed Model of Cyclostationary Noise in Switched-Resistor Circuits

“…It can be easily shown that the model in eq. ( 12) gives a reasonable accuracy only for duty cycle values higher than about 1 to 10%, even when the equivalent resistance obtained by the model in [29] is used. Integrated filters for biomedical and IoT devices often require high resistance values to implement the very large time constants needed to process the low frequency biological signals [30].…”

“…A duty-cycle-controlled clock is applied to the TG switch to set the average current that flows in the series. A detailed model of the S-R technique accounting also for parasitic capacitances and off-state resistances has been recently presented in [29] by the authors to accurately predict the equivalent resistance R eq of a S-R.…”

“…As an additional remark, it has to be noted that, using the approximation R p D in place of R eq results in an even higher error between predicted and simulated noise, due also to the poor estimation of R eq . In this paper, in order to develop a model, suitable to accurately describe the cyclostationary noise in S-R circuits, we start from the detailed model of the S-R technique presented in [29] and add to it the most relevant noise sources, thus obtaining the equivalent circuit reported in Fig. 7.…”

“…7. The detailed S-R model proposed in [29] is characterized, other than by the parasitic capacitance C p , also by a finite channel resistance in the off state, that significantly affects the average current flowing in the S-R at low duty cycles. Hence the equivalent circuit in Fig.…”

80 dB tuning range transimpedance amplifier exploiting the Switched-Resistor approach

“…The principle of operation of the SR technique can be described referring to Figure 2a For applications requiring a very small duty cycle in order to get a very high resistance multiplication factor, the parasitic elements become dominant, and an accurate model is required to determine the exact value of the duty cycle needed to obtain a specific value of the equivalent resistance. The equivalent resistance can be expressed as [20]:…”