The forward bias current conduction mechanisms of Au/PVC + TCNQ/p-Si structures have been investigated in a wide temperature range of 120-420 K for various applied bias voltage. The analysis of the main electrical parameters such as zero-bias barrier height (BH) ( Bo ), ideality factor (n), and interface states (N ss ) was found strongly dependent on temperature and voltage. The obtained results show that, while Bo increases, n decreases with increasing temperature. The plot of app versus q/2kT was drawn to show a Gaussian distribution (GD) of the BHs, and this plot shows two distinct linear regions. The Bo and standard deviation (σ s ) values were found from the slope and intercept of these plots for two regions as 1.16 eV and 0.161 V for the first region and 0.71 eV and 0.093 V for the second region, respectively. Such behavior is typical of a double GD (DGD) of the BHs due to the BH inhomogeneities at the metal-semiconductor interface. The slope and intercept of the modified (ln(I 0 /T 2 ) -q 2 σ 0 2 /2k 2 T 2 ) versus q/kT plot gives the and¯ Bo and effective Richardson constant (A*) as 1.16 and 0.76 eV and 36.7 and 83.8 A/cm 2 K 2 , respectively. The value of the A* (36.7 A/cm 2 K 2 ) is very close to the theoretical value of 32 A/cm 2 K 2 for p-Si. In addition, to interrupt the voltage-dependent activation energy, the ln(I s /T 2 ) versus q/kT plot was drawn in the voltage range of 0-0.3 V in 0.05 V steps. All of experimental results confirmed that the BH or E a values depend on the temperature as well as bias voltages. C