A development methodology for embedded systems based on RT-DEVS

Abstract

This work is concerned with modelling, analysis and implementation of embedded control systems using RT-DEVS, i.e. a specialization of classic discrete event system specification (DEVS) for real-time. RT-DEVS favours model continuity, i.e. the possibility of using the same model for property analysis (by simulation or model checking) and for real time execution. Special case tools are reported in the literature for RT-DEVS model analysis and design. In this work, temporal analysis of a model exploits a translation in Uppaal timed automata for exhaustive verification. For large models a simulator was realized in Java which directly stems from RT-DEVS operational semantics. The same concerns are at the basis of a real-time executive. The paper describes the proposed RT-DEVS development methodology and clarifies its implementation status. The approach is demonstrated by applying it to an embedded system example which is analyzed through model checking and implemented in Java. Finally, research directions which deserve further work are indicated.

Translation of UML Statecharts to UPPAAL Automata for Verification of Real-time Systems

“…We reproduced the results that were obtained manually in [4] with our automatic translation and showed that the tool is applicable to models of relatively simple real-time systems with parallel interacting processes. Further work includes formal proof of the correctness of the algorithm based on [3] and testing the tool on practical examples of real-time systems.…”

“…Some more complex tests were aimed to simulate the whole process of verification of a system defined by a UML statechart diagram. Below we present the results of our experiments with the model of traffic lights control system described in [4].…”

“…When a file is parsed and an internal representation is constructed, the translation is performed in two phases. First, the statechart is transformed to the intermediate form -an hierarchical timed automaton (HTA) [4] -and then this automaton is translated to a network of timed automata (NTA) according to the algorithm similar to the one introduced in [4].…”

“…In [4] the authors constructed a UPPAAL model for this system manually to verify its properties. We used our translator and obtained the model automatically.…”

Transforming Medical Best Practice Guidelines to Executable and Verifiable Statechart Models

“…Unfortunately, Yakindu does not provide formal verification capability. To bridge the gap between system modeling and formal verification, efforts are made from research community to transform system modeling specifications/languages, such as UML (unified modeling language) statecharts [13], [20], hierarchical timed automata (HTA) [5], discrete event system specification for real-time (RT-DEVS) [8], and parallel object-oriented specification language (POOSL) [18], to UPPAAL timed automata. Yakindu statecharts are similar to UML statecharts, but have major semantics differences [2].…”