A diagonal interconnect architecture and its application to RISC core design

Igarashi, M.; Mitsuhashi, T.; Le, A.D.T.; Kazi, S.; Lin, Yang-Trung; Fujimura, Aki; Teig, Steven

doi:10.1109/isscc.2002.992196

Cited by 28 publications

(18 citation statements)

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“…Moreover, a Y clock tree has a better total wire length compared to X clock tree structure without overlapping of parallel interconnect This simple analysis shows that the wirelength reduction caused by the "virtuous cycle" effect is significant, and can partly explain the large wirelength reductions reported in [15] and [31].…”

Section: Discussionmentioning

confidence: 89%

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The Y architecture for on-chip interconnect: analysis and methodology

Chen

Cheng²,

Kahng

et al. 2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Section: Discussionmentioning

confidence: 89%

“…For full commercial designs placed and routed with octilinear-aware tools, [15] and [31] report wirelength improvements of 20% or more.…”

Section: Wirelength Reductionmentioning

confidence: 99%

The Y architecture for on-chip interconnect: analysis and methodology

Chen

Cheng²,

Kahng

et al. 2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Because of the limitation of traditional 2D mesh topology, additional alternative routing resources which provide more network tolerance are employed to further improve the performance of the NePA architecture. Moreover, diagonal links for the 2D mesh network are proposed to improve throughput and performance because of the emergence of X-architecture routing technique in chip manufacturing [21,39]. The proposed NoC architecture referred to as Diagonally-linked Mesh (DMesh) employs diagonal express links among routers on a baseline NePA network [20].…”

Section: Introductionmentioning

confidence: 99%

Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip

Wang

Bagherzadeh

2014

Microprocessors and Microsystems

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a b s t r a c tThis paper proposes a novel QoS-aware and congestion-aware Network-on-Chip architecture that not only enables quality-oriented network transmission and maintains a feasible implementation cost but also well balance traffic load inside the network to enhance overall throughput. By differentiating application traffic into different service classes, bandwidth allocation is managed accordingly to fulfill QoS requirements. Incorporating with congestion control scheme which consists of dynamic arbitration and adaptive routing path selection, high priority traffic is directed to less congested areas and is given preference to available resources. Simulation results show that average latency of high priority and overall traffic is improved dramatically for various traffic patterns. Cost evaluation results also show that the proposed router architecture requires negligible cost overhead but provides better performance for both advanced mesh NoC platforms.

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“…Besides congestion, load misbalance also brings about hotspots [8] and thermal problems [11] in NoC. These problems have exerted negative effect not only on system performance, but also on the system reliability [12,13]. 8 Â 8 network, the value of Φ decreases 45% at least and the total network workload declines about 50% in various traffic patterns.…”

Section: Introductionmentioning

confidence: 99%