A Die-level Adaptive Test Scheme for Real-time Test Reordering and Elimination

Abstract

Semiconductor manufacturing companies aim to achieve shortest test times for products while maintaining the product quality. This thesis evaluates the performance of ATS with synthetic data generated by a Monte Carlo method and with production wafer sort data for two manufactured products. The product data results show ATS reduced by 20% the total test-time for one product and by 40% for a second product, with changes in product quality level below industry targets.