A Differential LNA Architecture with Improved Figure of Merit Using 40 nm UMC CMOS Technology for mmWave Band Receiver Applications

Verma, Ankit; Yadav, Pritesh Kumar; Goswami, Manish; Misra, Prasanna Kumar

doi:10.1007/s11277-021-09383-2

Cited by 2 publications

(1 citation statement)

References 28 publications

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“…The cascode structure can make the amplifier have the advantages of low noise, high gain, and easy matching. Many LNAs designed in papers adopt the cascode structure and add the source pole degradation inductance on this basis so that the inductance resonates with the parasitic transistor capacitance to realize the matching of the virtual part of the input impedance and optimize the noise coefficient [3][4][5][6]. The addition of source negative feedback inductance reduces the channel noise of the source but does not reduce the channel noise from the common-gate stage of the common-gate circuit, leading to the narrow circuit bandwidth.…”

Section: Introductionmentioning

confidence: 99%

An S-band MMIC LNA in GaAs 0.15-μm pHEMT

Liang,

2023

J. Phys.: Conf. Ser.

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The study adopts a monolithic microwave integrated circuit (MMIC) low-noise amplifier (LNA) applied in S-band was designed using ADS simulation software, GaAs 0.15-um pseudomorphic high electron mobility transistor (pHEMT) process. The LNA small signal gain is greater than 30.8 dB, gain flatness is ±0.45 dB, noise coefficient is less than 1.5 dB, input and output return loss is greater than 10 dB, and the chip area is 1.2*2.4 mm2. The low noise amplifier is composed of a two-stage cascade structure. Gain flatness, gain control, and bandwidth broadening are improved by RLC negative feedback network. The minimum noise coefficient circle and maximum gain circle are narrowed by adding negative feedback to achieve better noise coefficient and gain.

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Section: Introductionmentioning

confidence: 99%