A Digital Background Calibration Scheme for Pipelined ADCs Using Multiple-Correlation Estimation

Wu, Meng-Shuan; Hong, Hao-Chiao

doi:10.1109/iscas.2018.8351746

Cited by 7 publications

(3 citation statements)

References 10 publications

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“…Instead of directly setting IGE coefficients like in [15], [17], we have extracted the IGE related nonideal factors (the finite open loop gain, the finite bandwidth, and the finite slew rate) by amplifier pre-simulations. Besides, other nonideal factors including the capacitance mismatch, the amplifier offset, the comparator offset, the deviation of paired comparators tuned offset, the comparator noise, and the thermal noise are also considered.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…1, swing degradation is avoided in [13], [14], but the 3 rd -order IGE issue remains unsolved. Complexity of high-order (higher than 3 rd ) IGE calibration is reduced in [15], [17], but there still exist severe swing overheads. Suppression of swing deterioration for high-order IGE calibration is difficult as the high-order-distortion-dependent PN sequence has to be constructed to extract high-order IGE coefficient.…”

Section: Introductionmentioning

confidence: 99%

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Reducing Signal Swing Overheads to Only 8% in Background 3^rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs

Yang

Yin

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a correlation-based 3 rd -order inter-stage gain error background calibration technique for high-performance pipeline ADCs, with the reduced signal swing overhead to only 8% during the pseudo noise (PN) sequence injection. This is achieved by exploiting the use of paired comparators along with a dedicated calibration algorithm, namely the adaptive dither injection calibration (ADIC) technique, which further alleviates the trade-off between the signal-to-noise ratio and the non-linearity. Monte Carlo simulation results of a 16-bit 100MS/s ADC show that with an amplifier of 20dB loop gain, the spurious-free dynamic range (SFDR) is improved from 64.8dB to a mean value of 106.6dB and a standard deviation of 1.1dB.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Reducing Signal Swing Overheads to Only 8% in Background 3^rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs

Yang

Yin

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…If there is a mismatch between V PN1 and V PN2 , the formula [13] will introduce an additional estimation error and leading to incorrect computation results. Similarly, the algorithm described in [12] also fails to obtain the exact γ k .…”

mentioning

confidence: 99%

A digital background calibration technique for interstage gain nonlinearity in pipelined ADCs

Ding

Miao

et al. 2022

IEICE Electron. Express

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This paper presents a digital background technique that intentionally exploits multiple dithers to calibrate conversion errors caused by interstage gain error and nonlinearity in high speed pipelined analog-todigital converters (ADCs). Two independent, zero-mean pseudo-random signals are injected into the multiplying digital-to-analog converter (MDAC) alternately to estimate these errors. Least mean square (LMS) algorithms are adopted to quickly locate and track the calibration parameters. Simulation results are presented for a 800 MSps 12-bit pipelined ADC in a 40 nm CMOS technology , similar to that described by Murmann and Boser [1], Keane et al. [2] and Nan Sun [3] using low-gain amplifiers. With calibration, the signal-to-noise-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved from 32.74 dB and 43.61 dB to 70.54 dB and 89.8 dB, respectively. The proposed calibration technique has the advantages of simple implementation, arbitrary amplitude pseudo-random signals, and no restriction on the input signal of the ADC.

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Multipurpose error calibration of pipeline analog‐to‐digital converters using decision points of the residue curve in sub‐analog‐to‐digital converters

Ghanbari,

Farshidi,

Sheini

2024

Circuit Theory & Apps

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SummaryA new mechanism of digital background calibration in pipeline analog‐to‐digital converters (ADCs) is expressed. The presented technique calibrates various errors like capacitor mismatch, finite DC gain of the amplifier, third‐order nonlinearity, and fifth‐order nonlinearity, so it is called multipurpose. In this method, the error coefficients are identified by estimation of the output code of the decision points in the voltage transfer characteristic (VTC) of the pipeline stages. To achieve sufficient decision points in the VTCs of the pipeline stages, one threshold level of one comparator of the sub‐ADC is shifted, and then the digital output is calibrated by capturing the error coefficients. The digital logic of this method is simple and does not require special analog circuits. The introduced calibration mechanism is evaluated for the first five stages of a 12‐bit 100 MS/s pipeline ADC. The required time for the calibration is 1.5 ms. By applying this method, the signal‐to‐noise and distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) in order are enhanced from 46.44 and 50.53 dB to 69.92 and 74.04 dB, respectively.

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A Digital Background Calibration Scheme for Pipelined ADCs Using Multiple-Correlation Estimation

Cited by 7 publications

References 10 publications

Reducing Signal Swing Overheads to Only 8% in Background 3^rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs

Reducing Signal Swing Overheads to Only 8% in Background 3^rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs

A digital background calibration technique for interstage gain nonlinearity in pipelined ADCs

Multipurpose error calibration of pipeline analog‐to‐digital converters using decision points of the residue curve in sub‐analog‐to‐digital converters

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A Digital Background Calibration Scheme for Pipelined ADCs Using Multiple-Correlation Estimation

Cited by 7 publications

References 10 publications

Reducing Signal Swing Overheads to Only 8% in Background 3rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs

Reducing Signal Swing Overheads to Only 8% in Background 3rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs

A digital background calibration technique for interstage gain nonlinearity in pipelined ADCs

Multipurpose error calibration of pipeline analog‐to‐digital converters using decision points of the residue curve in sub‐analog‐to‐digital converters

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Reducing Signal Swing Overheads to Only 8% in Background 3^rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs

Reducing Signal Swing Overheads to Only 8% in Background 3^rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs