A digital calibration enhanced GSM/GPRS transmitter

Wang, Ping‐Ying; Wang, Ching-Hsing; Lee, Wei-Chi; Yu, Tai-Yun

doi:10.1109/rfic.2011.5940617

Cited by 5 publications

(2 citation statements)

References 11 publications

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“…Two-point modulators based on the ΔΣ fractional-N phaselocked loop (PLL) have been widely adopted in modern transmitters for various wireless standards such as GSM, Bluetooth, and ZigBee [1]- [4]. A 20Mb/s phase modulator based on the all-digital PLL (ADPLL) as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

A multi-bit FIR filtering technique for two-point modulators with dedicated digital high-pass modulation path

Rhee

Wen

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper describes an effective way of relaxing the nonlinearity problem of the digitally-controlled oscillator (DCO) in the two-point modulator design. A separate coarse varactor array dedicated for the high-pass modulation significantly simplifies the nonlinearity calibration of the DCO with a few-bit control. In addition, a finite-impulse response (FIR) filter is designed for the multi-bit high-pass modulation path to reduce the quantization noise, while offering a time-interleaving operation to minimize the DCO sensitivity to the coupling during switching time. A two-point modulator based on a semidigital fractional-N phase-locked loop (PLL) is implemented in 0.18μm CMOS. Simulation results show that the proposed modulator can achieve 10Mb/s GFSK/GMSK modulations with the EVM of -37dB.

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Section: Introductionmentioning

confidence: 99%

A multi-bit FIR filtering technique for two-point modulators with dedicated digital high-pass modulation path

Rhee

Wen

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

“…1 is a popular building block in modern transmitters such as Bluetooth, ZigBee and GSM systems [1]- [4]. However, there are three problems for two-point modulation structure: 1) gain mismatch; 2) digitally-controlled oscillator (DCO) nonlinearity; 3) delay mismatch.…”

Section: Introductionmentioning

confidence: 99%

A 10 Mb/s hybrid two-point modulator with front-end phase selection and dual-path DCO modulation

Liu

et al. 2015

2015 IEEE International Wireless Symposium (IWS 2015)

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This paper presents a hybrid two-point modulator for high data rate modulation. The two-point modulator utilizes a phase selection circuit with a high-frequency ΔΣ modulator (DSM) in low-pass modulation to achieve fine resolution for delay mismatch calibration. For high-pass modulation, a separate multi-bit path is designed for a digitally-controlled oscillator (DCO) in addition to the loop control path. A finite impulse response (FIR) filter is introduced in the high-pass modulation path to suppress quantization noise, while offering time-interleaving operation to mitigate the DCO sensitivity for each switching time. The proposed modulator is implemented in 65nm CMOS. Experimental results show that the modulator can achieve 10Mb/s GFSK modulation with the fine time resolution of 138ps.

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Impairment‐Aware Analog Circuit Design by Reconfiguring Feedback Systems

Wang

2012

Advanced Circuits for Emerging Technologies

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A digital calibration enhanced GSM/GPRS transmitter

Cited by 5 publications

References 11 publications

A multi-bit FIR filtering technique for two-point modulators with dedicated digital high-pass modulation path

A multi-bit FIR filtering technique for two-point modulators with dedicated digital high-pass modulation path

A 10 Mb/s hybrid two-point modulator with front-end phase selection and dual-path DCO modulation

Impairment‐Aware Analog Circuit Design by Reconfiguring Feedback Systems

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