A digital calibration technique for N-channel time-interleaved ADC based on simulated annealing algorithm

Zhang, Yuhao; Han, Chenxi; Liu, Shubin

doi:10.1016/j.mejo.2023.105701

Cited by 5 publications

(2 citation statements)

References 11 publications

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“…On using multiple AD converters in our FPGA system, a problem arises concerning the numerous conversion characteristics of each ADC and thus leading to probable measurement errors and inconsistencies. Te adopted solution stands on calibrating the ADCs and ensuring to get the same conversion characteristic or use high-quality ADCs [42].…”

Section: International Transactions On Electrical Energy Systemsmentioning

confidence: 99%

FPGA-Based Hardware in the Loop of Optimized Synergetic Controller for Active Power Filter

Bey

Krim

Gherouat

2023

International Transactions on Electrical Energy Systems

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This paper presents a discrete-time synergetic controller (DTSC) enhanced with ant colony optimization (ACO) technique for a shunt active power filter (SAPF). The developed controller is designed under MATLAB/Simulink environment; then, field-programmable gate array (FPGA) in the loop (FIL) technique is used to implement the DTSC model. The proposed DTSC parameters are optimally tuned according to ACO methodology. The DTSC-ACO should enhance power quality and eliminate grid current harmonics using an indirect current-controlled three-phase SAPF. Note that, the designed FPGA controller integrates the items needed to drive the SAPF. This digital implementation satisfies the hardware and recommended performance. In fact, it reduces significant resources and execution time. The experimental validation is carried out on Virtex-6 ML605 FPGA Xilinx Evaluation Kit using VIVADO processing. A total harmonic distortion (THD = 2.72%) is obtained for the grid current. Thus, the results obtained confirm proper operation of the developed approach. In addition, the proposed DTSC shows good dynamic performance during load step change and output voltage variation.

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Section: International Transactions On Electrical Energy Systemsmentioning

confidence: 99%

FPGA-Based Hardware in the Loop of Optimized Synergetic Controller for Active Power Filter

Bey

Krim

Gherouat

2023

International Transactions on Electrical Energy Systems

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“…Simulated annealing (SA) algorithm is a combinatorial optimization algorithm developed based on the study of the solid annealing process and the simulation of the process of reaching thermal equilibrium in solids at constant temperature inspired by Metropolis et al It is a stochastic optimization-seeking algorithm based on a Monte Carlo iterative solution strategy, and its starting point is based on the similarity between the solids annealing process and combinatorial optimization problems. 3 The simulated annealing algorithm uses the accumulated information to search the space to a certain extent, using a balanced strategy, while being able to retain certain inferior solutions to avoid local search traps.…”

Section: Principle and Steps Of Genetic Simulated Annealing Algorithmmentioning

confidence: 99%

Two-dimensional array antenna directional pattern optimization method based on genetic simulated annealing algorithm

Liu,

Chen,

Yuan

2023

Third International Conference on Advanced Algorithms and Signal Image Processing (AASIP 2023)

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The genetic simulated annealing algorithm is suitable for optimization problems in complex multidimensional space because of its strong global search capability and the fact that it does not easily fall into local optimal solutions. The simulation results show that the genetic simulated annealing algorithm can effectively improve the pattern optimization performance and reduce the computing time compared with the standard genetic algorithm.

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Exploring swarm intelligence optimization techniques for task scheduling in cloud computing: algorithms, performance analysis, and future prospects

Prity,

Uddin,

Nath

2023

Iran J Comput Sci

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A digital calibration technique for N-channel time-interleaved ADC based on simulated annealing algorithm

Cited by 5 publications

References 11 publications

FPGA-Based Hardware in the Loop of Optimized Synergetic Controller for Active Power Filter

FPGA-Based Hardware in the Loop of Optimized Synergetic Controller for Active Power Filter

Two-dimensional array antenna directional pattern optimization method based on genetic simulated annealing algorithm

Exploring swarm intelligence optimization techniques for task scheduling in cloud computing: algorithms, performance analysis, and future prospects

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