A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique

Kim, Hyung Seok; Ornelas, C.; Chandrashekar, Kailash; Shi, Dan; Su, Pin-En; Madoglio, Paolo; Li, W. Y.; Ravi, Ashoke

doi:10.1109/jssc.2013.2253407

Cited by 14 publications

(3 citation statements)

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“…For example, we estimated the clock frequencies corresponding to˜ tgt = 0.25 and˜ min = 0.125 for our 512-bit mixed architecture as approximately 1GHz and 950MHz, respectively. Reference [56] provide a clock signal in the GHz range with a frequency resolution of 100 Hz, which is orders of magnitude more accurate.…”

Section: Internal Chip Controlmentioning

confidence: 99%

Learning with Physical Noise or Errors

Kamel

Standaert

Duc

et al. 2020

IEEE Trans. Dependable and Secure Comput.

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Hard learning problems have recently attracted significant attention within the cryptographic community, both as a versatile assumption on which to build various protocols, and as a potentially sound basis for lightweight (possibly side-channel and fault resistant) implementations. Yet, in this second case, a recurrent drawback of primitives based on the Learning Parity with Noise and Learning With Errors problems is their additional randomness requirements to generate noise or errors. In parallel, the move towards nanoscale devices renders modern implementations increasingly prone to various types of errors. As a result, inexact computing has emerged as a new paradigm to efficiently deal with the challenges raised by such erroneous computations, and mitigate the cost and power consumption overheads they cause. In this paper, we show that these cryptographic and electronic challenges can actually be turned into new opportunities, and provide an elegant solution one to the other. That is, we show that inexact implementations of inner product computations lead to a natural way to define new Learning with Physical Noise or Error assumptions, paving the way to more efficient and physically secure implementations, with potential interest for securing emerging Internet of Things applications.

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Section: Internal Chip Controlmentioning

confidence: 99%

Learning with Physical Noise or Errors

Kamel

Standaert

Duc

et al. 2020

IEEE Trans. Dependable and Secure Comput.

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“…This behavior is obtained using the gated-ring-oscillator (GRO), proposed in [10]. Remarkable steps forward in this direction are the recent work in [11], which discusses and mitigates the issues related to the GRO design, and that in [12], which introduces a recirculating TDC based on a single delay cell. All of these solutions are effective to reduce the level of spurs induced by nonlinearity.…”

Section: A Conventional Digital Pllsmentioning

confidence: 99%

“…The time-to-digital converter (TDC) is typically the main source of such spurs, whose level is a function of the resolution and nonlinearity of its conversion characteristic. Several techniques have been proposed both to refine resolution and improve linearity [4]- [12]. Despite having achieved good results, most of these solutions consume more power than is desired or necessary.…”

mentioning

confidence: 99%

An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs

Levantino

Marzin²,

Samori

2014

IEEE J. Solid-State Circuits

106

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Digital fractional-N phase-locked loops (PLLs) are an attractive alternative to analog PLLs in the design of frequency synthesizers for wireless applications. However, the main obstacle to their full acceptance in the wireless-systems arena is their higher content of output spurious tones, whose level is ultimately set by the nonlinearity of the time-to-digital converter (TDC). The known methods to improve the linearity of the TDC either increase its dissipation and phase noise or require slow foreground calibrations. By contrast, the class of digital PLLs based on a one-bit TDC driven by a multi-bit digital-to-time converter (DTC) substantially reduces power dissipation and eliminates the TDC nonlinearity issues. Although its spur performance depends on DTC linearity, the modified architecture enables the application of a background adaptive pre-distortion which does not compromise the PLL phase-noise level and power consumption and is much faster than other calibration techniques. This paper presents a 3.6-GHz digital PLL in 65-nm CMOS, with in-band fractional spurs dropping from -39 to -52 dBc when the pre-distortion is enabled, in-band phase noise of -103 dBc/Hz and power con- sumption of 4.2 mW

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